- J. M. Rabaey, A. Chandrakasan, B. Nikolic,
*Digital Integarted Circuits: A Design Perspective*, 2^{nd}edition, Prentice-Hall, 2003.

- R. Winoto, B. Nikolić, “Discrete-time processing of RF signals,” in Advanced Techniques for Multi-Mode/Multi-Band RF Transceivers, G. Hueber and B. Staszewski, (eds.) Springer, 2009.
- L.-T. Pang, B. Nikolić, “Variability in deeply-scaled CMOS,” in Circuits at the Nanoscale: Communications, Imaging and Sensing, K. Iniewski, (ed.), CRC Press, 2008, pp. 25-37.
- B. Nikolic, M. Leung, E. Yeo, K. Fukahori, "Read/Write Channel Implementation,"
in
*Coding and Signal Processing for Recording*, B. Vasic, E. Kurtas (eds.) pp. 34-1 - 34-34, CRC Press, 2004. - K. Kuusilinna, C. Chang, H.-M. Bluethgen, W. R. Davis, B. Richards, B. Nikolic,
R. W. Brodersen, "Real Time System-on-a-Chip Emulation," in
*Winning the SoC Revolution*by H. Chang, G. Martin, Norwell, MA: Kluwer Academic Publishers, 2003. pp. 229-253. - D. Chinnery, B. Nikolic, K. Keutzer, "Achieving 550MHz in a Standard Cell ASIC
Methodology," in
*Bridging the Gap Between ASIC and Custom: Tools and Techniques for High-Performance ASIC Design,*D. Chinnery, K. Keutzer, Norwell, MA: Kluwer Academic Publishers, 2002, pp. 345-360.

- L.-T. Pang, K. Qian, C. Spanos, B. Nikolić, “Measurement and analysis of variability in 45nm strained-Si CMOS technology,” to appear in IEEE Journal of Solid-State Circuits, vol. 44, no. 9, August 2009.
- L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, B. Nikolić, “Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes,” to appear in IEEE Transactions on Information Theory, 2009.
- A. Carlson, Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. King Liu, B. Nikolić, “SRAM read / write margin enhancements using FinFETs,” to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009.
- Z. Zhang, L. Dolecek, B. Nikolić, V. Anantharam, M. J. Wainwright, “Design of LDPC decoders for improved low error rate performance: Quantization and algorithm choices,” to appear in IEEE Transactions on Communications, 2009.
- L. Dolecek, P. Lee, Z. Zhang, V. Anantharam, B. Nikolić, M. J. Wainwright, “Predicting error floors of structured LDPC codes: Deterministic bounds and estimates,” to appear in IEEE Journal of Selected Areas in Communications, 2009.
- L.-T. Pang, B. Nikolić, “Measurements and analysis of process variability in 90nm CMOS,” IEEE Journal of Solid-State Circuits, vol.44, no.5, pp. 1655-1663, May 2009.
- R. Zlatanovici, S. Kao, B. Nikolić, “Energy – delay optimization of 64-bit carry-lookahead adders with a 240ps 90nm CMOS design example,” IEEE Journal of Solid-State Circuits, vol. 44, no.2, pp.569-583, February 2009.
- B. Nikolic, "Design in the power-limited scaling regime,"
*IEEE Transactions on Electron Devices*, vol. 55, no. 1, pp. 71-83, January, 2008. (invited) - D. Markovic, B. Nikolic, R.W. Brodersen, "Power and Area Minimization for Multidimensional Signal Processing,"
*IEEE Journal of Solid-State Circuits*, vol. 42, no. 4, pp. 922-934, April 2007. - H.-I. Liu, V. Dai, A. Zakhor, and B. Nikolic, "Reduced Complexity Compression Algorithms for Direct-Write Maskless
Lithography Systems,"
*Journal of Microlithography, MEMS and MOEMS*, vol.6, no.1, pp. 013007-1 – 013007-12, Jan.-Mar. 2007. - J.M. Rabaey,
F. De Bernardinis, A. Niknejad, B. Nikolic, A. Sangiovanni-Vincentelli,
"Embedding Mixed-Signal Design in Systems-on-a-Chip,"
*Proceedings of the IEEE*, vol. 94, no. 6, pp. 1070-1088, June 2006.

- R. Zlatanovici, B. Nikolic, "Power-Performance Optimization for Custom Digital
Circuits,"
*Journal of Low Power Electronics*, vol. 2, no. 1, pp. 113-120, April 2006. - Y. Chiu, P.R. Gray, B. Nikolic, "A 14-bit, 12-MS/s CMOS Pipeline
ADC with over 100-dB SFDR,"
*IEEE Journal of Solid-State Circuits*vol. 39, no. 12, pp. 2139-2151, December 2004. - D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, "Methods for True Energy-Performance Optimization,"
*IEEE Journal of Solid-State Circuits*, vol. 39, no. 8, pp. 1282-1293, August 2004. - Y. Shimazaki, R. Zlatanovici, B. Nikolic, "A Shared-Well Dual-Supply-Voltage
64-bit ALU,"
*IEEE Journal of Solid-State Circuits*, vol. 39, no. 3, pp. 494-500, March 2004. - F. Ishihara, F. Sheikh, B. Nikolic, "Level-Conversion for Dual-Supply Systems,"
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol. 12, no.2, pp. 185-195, February 2004. - Y. Chiu, C. Tsang, B. Nikolic, P.R. Gray, "Least-Mean-Square Adaptive Digital
Background Calibration of Pipelined A/D Converters,"
*IEEE Transactions on Circuits and Systems, part I: Fundamental Theory and Applications*, vol. 51, no. 1, pp. 38-46, January 2004. - R. Lynch, E. Kurtas, A. Kuznetsov, E. Yeo, B. Nikolic, "The Search for a Practical
Iterative Detector for Magnetic Recording,"
*IEEE Transactions on Magnetics*, vol. 40, no. 1, pp. 213-218, January 2004. - E. Yeo, B. Nikolic, V. Anantharam, "Iterative Decoder
Architectures,"
*IEEE Communications Magazine*, vol. 41, no.8, pp. 132-140, August 2003. - E. Yeo, S. Augsburger, W.R. Davis, B. Nikolic, "A 500Mb/s Soft-Output Viterbi
Decoder,"
*IEEE Journal of Solid-State Circuits*, vol. 38, no. 7, pp. 1234-1241, July 2003. - W.R. Davis, N. Zhang, K. Camera, D. Markovic, T. Smilkstein, M.J.
Ammer, E. Yeo, S. Augsburger, B. Nikolic, R.W. Brodersen, "A Design
Environment for High Throughput, Low Power Dedicated Signal Processing
Systems,"
*IEEE Journal of Solid-State Circuits*, vol.37, no.3, pp. 420-431, March 2002. - B. Nikolic, M. Leung, L. Fu,
"Rate 8/9 Distance-Enhancing Code with Stationary Detector,"
*IEEE Transactions on Magnetics*, vol.37, no.3, pp. 1168-1174, May 2001. - M. Leung, B. Nikolic, L. Fu, T. Jeon,
"Reduced Complexity Sequence Detection for Higher Order Partial Response Channels",
*IEEE Journal of Selected Areas in Communications*, vol.19, no.4, pp.649-661, April 2001. - E. Yeo, P. Pakzad, B. Nikolic, V. Anantharam,
"VLSI Architectures for Iterative Decoders in Magnetic Recording Channels,"
*IEEE Transactions on Magnetics*, vol.37, no.2, pp.748-755, March 2001. - D. Markovic, B. Nikolic, V.G. Oklobdzija,
"A General Method in Synthesis of Pass-Transistor Circuits,"
*Microelectronics Journal*, vol. 31, no. 11-12, pp. 991-998, November 2000. - D. Maksimovic, V. Oklobdzija, B. Nikolic, K.W. Current, "Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply
,"
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol.8, no.4, pp. 460-463, August, 2000. - B. Nikolic, V. Stojanovic, V.G. Oklobdzija, W. Jia, J. Chiu, M. Leung,"Improved Sense Amplifier-Based Flip-Flop: Design and Measurements,"
*IEEE Journal of Solid State Circuits*, vol. 35, no.6, pp.876-884, June 2000. - B. Nikolic, D.V. Tosic, S. Marjanovic, "Symbolic Analysis of Feedback
Amplifier Circuits," (in Serbo-Croat),
*Tehnika: Elektrotehnika*, Vol. 45, No 7-8, pp. E1-E5, July/August 1996.

- 1. V. Nagpal, S. Pawar, D. Tse, B. Nikolić, “Cooperative multiplexing in the
multiple antenna half duplex relay channel,” to be presented at the
*2009 IEEE International Symposium on Information Theory*, Seoul, Korea, June 28 – July 3, 2009. - Z. Zhang, V. Anantharam, M. J. Wainwright, B. Nikolić, “A 47 Gb/s
LDPC decoder with improved low error rate performance,” to be presented at the
*2009 Symposium on VLSI Circuits*, Kyoto, Japan, June 16-18, 2009. - R. Winoto, B. Nikolić, “A highly reconfigurable 400-1700MHz receiver using a
down-converting sigma-delta A/D with a 59-dB SNR, and 57-dB SFDR over 4-MHz
bandwidth,” to be presented at the
*2009 Symposium on VLSI Circuits*, Kyoto, Japan, June 16-18, 2009. - K. Qian, B. Nikolić, C. Spanos, “Hierarchical modeling of spatial
variability with a 45nm example,”
*Proc. SPIE 7275*, San Jose, CA, February 22-27, 2009, pp. 727505-1-727505-12. - L. T.-N. Wang, L.-T. Pang, A. R. Neureuther, B. Nikolić, “Parameter-specific
electronic measurement and analysis of sources of variation using ring
oscillators,”
*Proc. SPIE 7275*, San Jose, CA, February 22-27, 2009, pp. 72750L-7275L-10. - Z. Zhang, L. Dolecek, B. Nikolić, V. Anantharam, M. J. Wainwright, “Lowering
LDPC error floors by postprocessing,”
*Proc. IEEE Globecom 2008*, New Orleans, LA, November 30 – December 4, 2008. - L.-T. Pang, B. Nikolić, “Measurement and analysis of variability in 45nm
strained-Si CMOS technology,”
*Proc. 2008 Custom Integrated Circuits Conference, CICC’2008*, San Jose, CA, September 21-24, 2008, pp. 129-132. - A. Carlson, Z. Guo, L.-T. Pang, T.-J. King Liu, B. Nikolić, “Compensation of
systematic variations through optimal biasing of SRAM wordlines,”
*Proc. 2008 Custom Integrated Circuits Conference, CICC’2008*, San Jose, CA, September 21-24, 2008, pp. 411-414. - C. Tsang, Y. Chiu, J. Vanderhaegen, S. Hoyos, C. Chen, R. Brodersen, B.
Nikolić, “Background ADC calibration in digital domain,”
*Proc. 2008 Custom Integrated Circuits Conference, CICC’2008*, San Jose, CA, September 21-24, 2008, pp. 301-304. - S. Hoyos, C. Tsang, J. Vanderhaegen, Y. Chiu, Y. Aibara, H. Khorramabadi, B.
Nikolić, “A 15 MHz – 600 MHz, 20 mW, 0.38mm2, Fast coarse locking digital DLL in
0.13m CMOS,”
*Proc. 34th European Solid-State Circuits Conference, ESSCIRC 2008*, Edinburgh, Scotland, September 15-19, 2008, pp. 90-93. - T. Oshima, T. Takahashi, T. Yamawaki, C. Tsang, D. Stepanovic, B. Nikolic,
“Fast nonlinear deterministic calibration of pipelined A/D converters,”
*Proc. 51st Midwest Symposium on Circuits and Systems, MWSCAS’2008*, August 10-13, 2008, pp. 914-917. - P. Lee, L. Dolecek, Z. Zhang, V. Anantharam, B. Nikolić, M. Wainwright,
“Error floors in LDPC codes: fast simulation, bounds and hardware emulation,”
*Proc.2008 IEEE International Symposium on Information Theory*, Toronto, ON, Canada, July 6-11, 2008, pp. 444-448. - Z. Guo, A. Carlson, L.-T. Pang, K. Duong, T.-J. King Liu, B. Nikolić,
“Large-scale read/write margin measurement in 45nm CMOS SRAM arrays,”
*2008 Symposium on VLSI Circuits, Dig. Tech Papers*, Honolulu, HI, June 18-20, 2008. pp. 42-43. - L. T.-N Wang, W.J. Poppe, L.-T. Pang, A.R. Neureuther, E. Alon, B. Nikolic,
“Hypersensitive parameter-identifying ring oscillators for lithography process
monitoring,”
*Proc. SPIE 6925*, Santa Clara, CA, February 2008, pp. 69250P-1 – 69250-10. - B. Nikolić, “Power-limited design,”
*Proc. 14th International Conference on Electronics, Circuits and Systems, ICECS’07*, Marrakech, Morocco, December 11-14, 2007, pp. 927-930. (invited) - B. Nikolić, “Towards efficient spectrum sharing,”
*Proc. Sixth IEEE Dallas Workshop on Circuits and Systems, DCAS’07*, Dallas, TX, November 2007, pp. 33-38. (invited) - Z. Zhang, R. Winoto, A. Bahai, B. Nikolic, "Peak-to-Average Power Ratio Reduction
in an FDM Broadcast System,"
*Proc. IEEE 2007 Workshop on Signal Processing Systems, SIPS 2007*, Shanghai, China, October 17-19, 2007. pp. 25-30. - Markovic, C. Chang, B. Richards, H. So, B. Nikolic, R.W. Brodersen, "
ASIC design and verification in an FPGA environment,"
*Proc. IEEE Custom Integrated Circuits Conference, CICC’07*, San Jose, CA, Sept. 16-19, 2007, pp. 737-740. - L. Dolecek, Z. Zhang, M. Wainwright, V. Anantharam, B. Nikolic, "Evaluation of the low frame error rate performance
of LDPC codes using importance sampling,"
*Proc. 2007 IEEE Information Theory Workshop, ITW’07*, Lake Tahoe, CA, Sept. 2-6, 2007. - Z. Zhang, L. Dolecek, M. Wainwright, V. Anantharam, B. Nikolic, "Quantization effects in low-density parity-check
decoders,"
*Proc. IEEE International Conference on Communications, ICC’07*, Glasgow, Scotland, June 24-27, 2007, pp. 6231-6237. - L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, B. Nikolic, "Analysis
of absorbing sets for array-based LDPC codes,"
*Proc. IEEE International Conference on Communications, ICC’07*, Glasgow, Scotland, June 24-27, 2007, pp. 6261-6268. - Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, M. Wainwright, “Investigation
of error floors of structured low-density parity-check codes
by hardware emulation,"
*Proc. IEEE GLOBECOM 2006*, San Francisco, CA, November 27 – December 1, 2006. - D. Fang, R. Roberts, B. Nikolic, "A 6-b DAC and analog DRAM for a maskless
lithography interface in 90nm CMOS,"
Proc. IEEE Asian Solid-State Circuits Conference, Hangzhou, China, November 13-15, 2006. pp. 423-426.
- A. Parsons, D. Backer, C. Chang, D. Chapman, H. Chen, P. Crescini, C. de Jesus, C. Dick, P. Droz, D. MacMahon, K. Meder,
J. Mock, V. Nagpal, B. Nikolic, A. Parsa, B. Richards, A. Siemion, J. Wawrzynek, D. Werthimer, M. Wright,
"PetaOp/Second FPGA Signal Processing for SETI and Radio Astronomy,"
*Proc. Asilomar Conference on Signals, Systems, and Computers*, Pacific Grove, CA, October 29-November 1, 2006. (invited). pp. 2031-2035. - F. Sheikh, M. Ler, R. Zlatanovici, D. Markovic, B. Nikolic, "
Power-performance optimal DSP architectures and ASIC
implementation,"
*Proc. Asilomar Conference on Signals, Systems, and Computers*, Pacific Grove, CA, October 29-November 1, 2006. pp. 1480-1485.(invited) - B. Nikolic, L.T. Pang, "Measurements and analysis of process variability in 90nm CMOS,
"
*Proc. 8th International Conference on Solid-State and Integrated Circuit Technology*, Shanghai, China, October 23-26, 2006. (invited), pp. 505-508. - A. Carlson, Z. Guo, S. Balasubramanian, L.-T. Pang, T.-J. King Liu, B. Nikolic, "
FinFET SRAM with enhanced
read/write margins,"
*Proc. IEEE International SOI Conference*, Niagara Falls, NY, October 2-5, 2006. pp. 105-106. - D. Markovic,
R.W. Brodersen, B. Nikolic, ”A 70GOPS, 34mW Multi-carrier MIMO chip in 3.5mm
^{2},"*2006 Symposium on VLSI Circuits, Digest of Technical Papers*, Honolulu, HI, June 15-17, 2006. pp. 196-197. - S. D.
Vamvakos, V. Stojanovic, J. L. Zerbe, C. W. Werner, D. Draper, B. Nikolic, "PLL
on-chip jitter measurement: Analysis and design,"
*2006 Symposium on VLSI Circuits, Digest of Technical Papers*, Honolulu, HI, June 15-17, 2006. pp. 90-91. - C.W. Tsang,
Y. Chiu, B. Nikolic, "1.2V, 10.8mW, 500kHz Sigma-delta modulator with 84dB
SNDR and 96dB SFDR,"
*2006 Symposium on VLSI Circuits, Digest of Technical Papers*, Honolulu, HI, June 15-17, 2006. pp. 202-203. - L.T. Pang, B.
Nikolic, "Impact of layout on 90nm CMOS
process parameter fluctuations,"
*2006 Symposium on VLSI Circuits, Digest of Technical Papers*, Honolulu, HI, June 15-17, 2006. pp. 84-85. - D. Markovic, B.Nikolic, R.W.Brodersen, "Power and area efficient
VLSI architectures for communications signal processing,"
*Proc. IEEE International Conference on Communications, ICC'2006*, Istanbul, Turkey, June 11-15, 2006. pp. 3323-3328. - H.-I. Liu, V.Dai, A. Zakhor, B. Nikolic, "Reduced complexity
compression algorithms for direct-write maskless lithography systems,"
Proc. SPIE, vol. 6151, San Jose, CA, February 19-24, 2006, pp.
61512B-1-14.
- S. Kao, R.
Zlatanovici, B. Nikolic, "A 250ps 64-bit Carry-Lookahead
Adder in 90nm CMOS," 2006
*IEEE International Solid-State Circuits Conference*,*ISSCC’06*,*Digest of Technical Papers,*San Francisco, CA, February 4-8. 2006. pp. 438-439, 664. - E.Yeo, B.
Nikolic, "A 1.1-Gb/s 4092-bit low-density parity-check
decoder,"
*IEEE Asian Solid-State Circuits Conference*, Hsinchu, Taiwan, November 1-3, 2005. pp. 237-240. - R. Zlatanovici,
B. Nikolic, "Power-performance optimization for custom
digital circuits,"
*Proc. PATMOS’05, LNCS 3728*, Leuven, Belgium, September 20-23, 2005. pp. 404-414. - Y. Chiu,
B. Nikolic, P.R. Gray, "Scaling of
analog-to-digital converters into ultra-deep-submicron CMOS,"
*Proceedings, 2005 IEEE Custom Integrated Circuits Conference*, Sam Jose, CA, September 17-21, 2005, pp. 375-382. (invited). - Z. Guo, S.
Balasubramanian, R. Zlatanovici, T.-J. King, B. Nikolic,"FinFET-based SRAM design,"
*Design, ISLPED’05*, San Diego, CA, August 8-10, 2005, pp. 2-7. (Best paper award). - S. Balasubramanian, J. L. Garrett, V.
Vidya, B. Nikolic, T.-J. King, "Energy-Delay Optimization of Thin-Body MOSFETs
for the Sub-15 nm Regime,"
*Proc.**IEEE SOI Conference*2004, Charleston, SC, October 4-7, 2004. pp. 27-29. - E. Liao, E. Yeo, B. Nikolic, "Low-density parity-check code
constructions for hardware implementation,"
*Proceedings 2004 IEEE International Conference on Communications*, ICC'04, Paris, France, June 20-24, 2004, pp. 2573-2577. - S.D. Vamvakos, C. Werner, B. Nikolic, "Phase-locked loop
architecture for adaptive jitter optimization,"
*Proceedings of the 2004 IEEE International Symposium on Circuits and Systems (ISCAS'04)*, vol. IV, Vancouver, BC, Canada, May 23-26, 2004, pp. IV-161 - IV-164. - B. Nikolic, B. Wild, V. Dai, Y. Shroff, B. Warlick, A. Zakhor, W. Oldham,
"Layout decompression chip for maskless lithography,"
*Proc. of SPIE*, Vol. 5374, Santa Clara, CA, Feb. 24-26, 2004. - B. Warlick, B. Nikolic, "Mixed-signal data interface for maskless lithography,"
*Proc. of SPIE*, Vol. 5374, Santa Clara, CA, Feb. 24-26, 2004. - Y. Chiu, P.R. Gray, B. Nikolic, "
A 1.8-V, 14-b, 10-MS/s Pipelined ADC in 0.18-µm CMOS with 99-dB SFDR,"
*IEEE International Solid-State Circuits Conference, ISSCC'04*,*Digest of Technical Papers*, San Francisco, CA, February 14-19. 2004. pp. 458-459, 539. - R. Zlatanovici, B. Nikolic, "Power-Performance Optimal 64-bit
Carry-Lookahead Adders,"
*Proceedings of the 29*, September 16-18, 2003, Estoril, Portugal, pp. 321-324.^{th}European Solid-State Circuits Conference, ESSCIRC'03 - B. Nikolic, L. Chang, T.-J. King, "Performance of Deeply-Scaled,
Power-Constrained Circuits," 2003
*International Conference on Solid State Devices and Materials, SSDM 2003*, Tokyo, Japan, September 16-18, 2003, pp. 154-155. (invited). - F. Ishihara, F. Sheikh, B. Nikolic, "Level Conversion for Dual
Supply Systems,"
*Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'03*, Seoul, Korea, August 25-27, 2003. pp. 164-167. - R. Lynch, E. Kurtas, A. Kuznetsov, E. Yeo, B. Nikolic, "The Search
for a Practical Iterative Decoder for Magnetic Recording,"
*Digests of the 2003 Magnetic Recording Conference, TMRC'03*, Santa Clara, CA, August 18-20, 2003, p. B1. - C. Chang, K. Kuusilinna, B. Richards, A. Chen, N. Chan, R.W. Brodersen, B. Nikolic, "Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment, Proceedings 14th IEEE International Workshop on Rapid Systems Prototyping, San Diego, CA, June 9-11, 2003, pp. 148-154
- S. Balasubramanian, L. Chang, B. Nikolic, T.-J. King,
"Circuit-Performance Implications for Double-Gate MOSFET Scaling Below
25nm,"
*2003 Silicon Nanoelectronics Workshop*, Kyoto, Japan, June 8-9, 2003. - Y. Shimazaki, R. Zlatanovici, B. Nikolic, "A Shared-Well
Dual-Supply-Voltage 64-bit ALU," 2003
*IEEE International Solid-State Circuits Conference, ISSCC'03, Digest of Technical Papers*, San Francisco, CA, February 9-13, 2003, pp. 104-105, 481. - R.W. Brodersen, M.A. Horowitz, D. Markovic, B. Nikolic, V.
Stojanovic, "Methods for True Power Minimization,"
*International Conference on Computer-Aided Design, ICCAD-2002, Digest of Technical Papers*, San Jose, CA, November 10-14, 2002, pp. 35-42. (invited). - E. Yeo, S. Augsburger, W.R. Davis, B. Nikolic, "Implementation of
High-Throughput Soft-Output Viterbi Decoders,"
*IEEE Workshop on Signal Processing Systems, SIPS'02*, San Diego, CA, October 16-18, 2002. - V. Stojanovic, D. Markovic, B. Nikolic, M.A. Horowitz, R.W.
Brodersen, "Energy-Delay Tradeoffs in Combinational Logic using Gate
Sizing and Supply Voltage Optimization,"
*Proceedings of the 28*, Florence, Italy, September 24-26, 2002. pp. 211-214.^{th}European Solid-State Circuits Conference, ESSCIRC'2002 - E. Yeo, S. Augsburger, W.R. Davis, B. Nikolic, "A 500Mb/s
Soft-Output Viterbi Decoder,"
*Proceedings of the 28*, Florence, Italy, September 24-26, 2002. pp. 523-526.^{th}European Solid-State Circuits Conference, ESSCIRC'2002 - S. Augsburger, B. Nikolic, ""Reducing Power with Dual-Supply,
Dual-Thresholds and Transistor Sizing,"
*Proceedings IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD'02*, Freiburg, Germany, September 16-18, 2002. - E. Yeo, B. Nikolic, V. Anantharam, ""Architectures and
Implementation of Low-Density Parity-Check Decoding Algorithms,"
*45th IEEE Midwest Symposium on Circuits and Systems, MWSCAS 2002*, Tulsa OK, August 4-7, 2002. (invited). - E. Yeo, P. Pakzad, B. Nikolic, V. Anantharam, "High Throughput
Low-Density Parity-Check Decoder Architectures,"
*Proceedings 2001 Global Conference on Communications, Globecom'01*, San Antonio, TX, November 25-29, 2001. pp. 3019-3024. - D. Petrovic, B. Nikolic, K. Ramchandran, "List Viterbi Decoding
with Continuous Error Detection for Magnetic Recording Channels,"
*Proceedings 2001 Global Conference on Communications, Globecom'01*, San Antonio, TX, November 25-29, 2001. pp. 3007-3011. - W.R. Davis, N. Zhang, K. Camera, D. Markovic, T. Smilkstein, N.
Chan, M.J. Ammer, E. Yeo, B. Nikolic, R.W. Brodersen, "An Automated
Design Flow for Low-Power, High-Throughput Dedicated Signal Processing
Systems,"
*Thirty-Fifth Asilomar Conf. on Signals, Systems and Computers, Conf. Record*, vol. 1, Pacific Grove, CA, November 4-7, 2001. pp.475-480. - D. Markovic, B. Nikolic, R.W. Brodersen, "Analysis and Design of Low-Energy Flip-Flops,"
*Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design*, ISLPED'01, Huntington Beach, CA, August 6-7, 2001, pp.52-55. - D. Chinnery, B. Nikolic, K. Keutzer, "Achieving 550MHz in an ASIC Methodology,"
*Proceedings of the 38*, DAC'2001, Las Vegas, NV, June 18-22, 2001, pp. 420-425.^{th}Design Automation Conference - W.R. Davis, N. Zhang, K. Camera, F. Chen, D. Markovic, N. Chan, B. Nikolic, R.W. Brodersen,
"A Design Environment for High Throughput, Low Power, Dedicated Signal Processing Systems,"
*Proceedings of the IEEE Custom Integrated Circuits Conference,*CICC'2001, San Diego, CA, May 6-9, 2001. pp. 545-548. - J.L. da Silva, Jr, J. Shamberger, M.J. Ammer, C. Guo, S.-F. Li, R. Shah, T.Tuan, M. Sheets, J.M. Rabaey, B. Nikolic, A. Sangiovanni-Vincentelli, P. Wright, "Design Methodology for PicoRadio Networks,"
*Design, Automation and Test in Europe*,*DATE*'2001, Munich, Germany, March 13-16, 2001, pp.314-323. - E. Yeo, P. Pakzad, B. Nikolic, V. Anantharam, "VLSI Architectures for Iterative Decoders in Magnetic Recording Channels,"
*Digests of The Magnetic Recording Conference*,*TMRC*2000,*on Magnetic Recording Systems*, Santa Clara, CA, August 14-16, 2000, p. E6. - J. Popovic, B. Nikolic, K. W. Current, A. Pavasovic, D. Vasiljevic, "Low-Power CMOS RC Oscillators Based on Current Conveyors,"
*Proceedings of the*22^{nd}*IEEE International Conference on Microelectronics*,*MIEL*'2000, Nis, Yugoslavia, May 14-17, 2000, pp.691-694. - D. Markovic, B. Nikolic, V.G. Oklobdzija, "General Method in Synthesis of Pass-Transistor Circuits,"
*Proceedings of the*22^{nd}*IEEE International Conference on Microelectronics*,*MIEL*'2000, Nis, Yugoslavia, May 14-17, 2000, pp. 695-698. - B. Nikolic,
M. Leung, L. Fu, V.G. Oklobdzija, R. Yamasaki, "Reduced Complexity Sequence Detection for E
^{2}PR4 Magnetic Recording Channel," 1999.*IEEE Global Conference on Communications*,*GLOBECOM'99*,*Conference Record*, vol. 1, part B, Rio de Janeiro, Brazil, December 5-9, 1999, pp. 960-964. - B. Nikolic, V.G. Oklobdzija, "Design and optimization of sense amplifier-based flip-flops,"
*Proceedings of the 25*, Duisburg, Germany, September 21-23, 1999, pp. 410-413.^{th}European Solid-State Circuits Conference, ESSCIRC'99 - B. Nikolic, M. Leung, L.Fu, "A Rate 8/9 Sliding Block Code with Stataionary Detector for Magnetic Recording,"
*Proceedings*1999*International Conference on Communication*, ICC'99, vol. 3, Vancouver, BC, Canada, June 6-10, 1999, pp. 1653-1657. - B. Nikolic, V. Stojanovic, V.G. Oklobdzija, W. Jia, J. Chiu, M. Leung, "Sense Amplifier-Based Flip-Flop," 1999
*IEEE International Solid-State Circuits Conference, ISSCC*'99,*Digest of Technical Papers*, San Francisco, CA, February 15-17, 1999, pp. 282-283, 468. - J. Popovic, B. Nikolic, K. W. Current, A. Pavasovic, D. Vasiljevic, "CMOS Implementation of Low-power Oscillators Based on the Modified Fabre-Normand Current Conveyor,"
*Proceedings*1998.*International Conference on Electronics, Circuits and Systems, ICECS-98*, vol 2, Lisbon, Portugal, September 7-10, 1998, pp. 349-352. - B. Nikolic, S. Marjanovic, "A General Method of Feedback Amplifier Analysis,"
*Proceedings of the*1998*IEEE International Symposium on Circuits and Systems (ISCAS 98)*, vol. III, Monterey, CA, May 31 - June 3, 1998, pp. 415-418. - B.Nikolic, V.G. Oklobdzija, "Low Voltage BiCMOS TSPC Latch for High
Performance Digital Systems, "
*Proceedings of the*1998*IEEE International Symposium on Circuits and Systems (ISCAS'98)*, vol. II, Monterey, CA, May 31 - June 3, 1998, pp. 53-56. - D. Maksimovic, V. Oklobdzija, B. Nikolic, K.W. Current, "Clocked CMOS
Adiabatic Logic with Integrated Single-Phase Power-Clock Supply: Experimental
Results,"
*Proceedings 1997. International Symposium on Low-Power Electronics and Design*, Monterey, CA, August 18-20, 1997, pp. 323-327. Reprinted in*High-Performance System Design: Circuits and Logic*, IEEE Press 1999. - B. Nikolic, V. Oklobdzija, "A Single-Phase Clock High-Performance
BiCMOS Latch, "7
97, Singapore, Singapore, 10-12 September 1997.^{th}International Symposium on IC Technology, Systems, & Applications, ISIC- - D. Maksimovic, V. Oklobdzija, B. Nikolic, K.W. Current, "Design and
Experimental Verification of a CMOS Adiabatic Logic with Single-Phase
Power-Clock Supply,"
*Proceedings of the*40, Sacramento, CA, August 3-6, 1997, pp. 417-420.^{th}Midwest Symposium on Circuits and Systems - B. Nikolic, D.V. Tosic, S. Marjanovic, "Symbolic Analysis of Feedback
Amplifier Circuits",
*Proc.*4Leuven, Belgium, October 10-11, 1996, pp. 244-247.^{th}International Workshop on Symbolic Methods and Applications to Circuit Design, - B. Nikolic, B. Ristic, S. Marjanovic, "Data Transmission System Over
Electric Power Distribution Circuits," (in Serbo-Croat), II
*TELFOR Symposium*, Belgrade, Yugoslavia, 1994, pp. 258-261. - B. Ristic, B. Nikolic, S. Kovacevic, S. Marjanovic, "Data Transmission
Modem Over Electric Power Distribution Circuits," (in Serbo-Croat), XXXVIII
*ETRAN Conference*, Vol. II pp. Nis, Yugoslavia, 1994, pp. 79-80. - B. Nikolic, D. Vujadinovic, B. Ristic, S. Marjanovic, "Remote Power Meter Reading System," (in Serbo-Croat), XXXVIII
*ETRAN Conference*, Vol. II, Nis, Yugoslavia, 1994, pp. 77-78. - B. Nikolic, S. Kovacevic, B. Ristic, S. Marajanovic, "Power Distribution Circuits as a Communications Medium," (in Serbo-Croat), XXXVII
*ETAN Conference*, Vol. II - E, pp. 51-56, Belgrade, Yugoslavia, 1993, pp. 51-56.