EE290A: Advanced Topics in CAD
Component-Based Design of Electronic Systems

Homework 1: Estimating the Implementation of  JPEG (due Tuesday 2nd Feb, 5:00pm)

In this first homework, you will work in teams of one or two to evaluate one of a variety of approaches to the implementation of JPEG, as defined by the JavaTime specification provided. Implementation styles from hardware (standard cells), to software on a general-purpose processor, to software on a DSP will be considered and compared. Your results will be presented as an on-line summary and will be discussed with the group  in the third week of classes.

Evaluation of the design should be done using following metrics:

1. Performance: the speed of the implementation, e.g. secs/frame
2. Power: how much power is used to perform the computation, e.g. mW/frame
3. Cost: how many resources were used, e.g. area, number of transistors of a hardware implementation, code size of software involved, cost of standard part being used, etc...
4. Design effort/design time (staff months and wall-clock time)

Specification of the JPEG compression standard and a description can be found here. An example proposal for the analysis of the implementation of JPEG in Java can be found here. For evaluation purposes a frame can be considered as:

• 640x480 image
• 24 bits full color

In class, we will allocated specific groups to specific implementation approaches, from all hardware to all software on a general-purpose processor.

Submission details can be found here

Submissions:

• ARM
• ARM+ASIC
• ASIC
• DSP
• Tensilica

The summary can be found here

Homework 2: Search for Some Components (due Thursday 11th Feb, 5:00pm)

As a group, we will search the Web (and other resources) to find some interesting examples of components for us all to review. A few example are:

• Power PC core: 3.1 mm2 in 0.35u
• ARM core: 3.8 mm2 inc 0.35u
• MPEG2 Decoder: ~65k gates
• PCI Bus: ~8k gates
• Ethernet MAC: ~7k gates (soft)
• RSA Encryption: ~7k gates
• etc...

In general, anything that is useful in System-on-chip (SOC) design should be investigated. Information should include details such as:

• Description
• Performance
• Power
• Cost: ($,area,...)
• Use Model: hard/firm/soft, programmable/reconfigurable
• Source of information

You should get as much detail as possible from the IP provider, and state reasons for why you think this is/isn't a useful block (e.g. good/bad docs, easy/hard to incorporate or program, low/high cost, implements a much needed functionality in SOC, easy/hard to reuse across process generations...), and suggestions for modification of IP specs if it isn't.

Submission details can be found here

Submissions:

• ASC
• DES
• DSP
• Ethernet
• Microcontroller
• PCI
• Viterbi+Mpy+Ethernet
• Viterbi

Project: Viterbi

In this project each group will select a particular style of implementation of the Viterbi decoder.

Some of the parameters that have been decided upon are:

• uncoded word length = 1
• coded word length (n) = 2
  this means that it is rate 1/2
• constraint length (K aka. L) = 7
  this means that the number of states in trellis is 2^(K-1) or 64 states
• branch metric calculation is QPSK
  this means 4 transitions for each state and 64x4=256 total transitions
• soft decision wordlength (q) = 6
• chain-backing depth (D) = 96
• generator polynomials: p0 = 171, p1= 133 (octal)
  this means that p0=1111001, p1=1011011
• data rate 100 kbs
• goal: bit error rate (BER) = 10^-4
• signal to noise ratio (SNR) degradation 0.05dB

A simulator/specification for the Viterbi decoder can be found here.

The different phases of this project are:

• Phase One - Estimation (due Thursday, March 11th, 5:00pm)
  Each group will estimate their implementation style (as was done in HW#1).
  Submissions:
  • ARM
  • ASIC
  • CP
  • DSP
• Phase Two - Implementation (due Wednesday, May 5th, 5:00pm)
  Each group will carry their component through to a complete implementation, with well-defined interfaces and a detailed specification and set of design constraints.
• Phase Three - Evaluation (due last week of classes)
  Each group will particpate in the evaluation of the components we have created, pulling together our shared notions of what a component is (and is not!), and the various key issues involved in making a component-based design approach work. (pdf) (xls)
  • ASIC
  • CP (ppt)
  • DSP
  • ARM (pdf)

  The final report is here.