Prospective IP Search

EECS 290A Homework #2 4/11/99 Rhett Davis

Summary

	Multiplier	Viterbi Decoder	Viterbi Decoder	Viterbi Decoder	Ethernet PHY Core
Company	NTNU	SICAN-Microelectronics	Mentor/Inventra & IBM	Hantro Products Oy	Mysticom
Block Type	Soft	Soft	Soft	Soft	Hard + Soft
Performance	-	-	0.8 - 85 Msps	45 MHz	-
Technology	-	-	0.5 um (Mentor) 1.8V, 0.25um (IBM)	Altera FPGA	3.3V, 0.35 um
Size	to be counted	-	3200-34000 gates	500 LC's, 5120 RAM bits	-
Cost	free	~$100,000	negotiable	-	negotiable
Includes	HDL source	HDL source, test bench, support services	HDL Source, targeted for IBM's 0.25 um process	HDL Source, test-bench, test vectors, synth. scripts	GDSII for hard portion, Netlist & SDF for soft portion
Contact Info	-	Andy Karsten (650) 871-1494	Marnie Mar (at IBM) (650) 966-6703	-	Debbie Vogt (650) 520-7656

Sources

Most examples were found using the Electronic Design Technology & News Network (EDTN) Virtual Components Yellow Pages.

Multiplier
NTNU - Norwegian University of Science and Technology

source code

One block which often takes a long time to build is a multiplier. The EDTN Yellow-Pages had one reference to a Multiplier IP block, which turned out to be a web engine that generates VHDL or Verilog source on demand. The source for a Booth-encoded multiplier with 2 pipeline stages is given above.

It would be helpful for ASIC designers to be able to drop multipliers into a design in much the same way that a standard cell can be used, and perhaps this kind of generator is a step in that direction.

Viterbi Decoder
SICAN Microelectronics

SICAN Microelectronics offers this Viterbi decoder core and mentions it on their web site but offers no information on it. I talked briefly with Andy Karsten at SICAN. He informed me that they offer the source code for around $100,000 and support services for customers (primarily fabless semiconductor houses) to integrated it into their process and get it functioning properly. He said that they get such different results with each customer that posting data sheets and area/power/speed characterization info does not give an accurate idea of the decoder's capabilities.

Viterbi Decoder
Mentor/Inventra
Repackaged by IBM

Mentor Graphics/Inventra offers a Viterbi decoder core which IBM repackages and offers as a block for use with their "Blue Logic" fabrication services. I spoke with Marnie Mar at IBM who told me that their customers are still so few and far between that no immediate dollar value can be given to the Viterbi decoder core. Customers generally negotiate for a "Design Kit" which includes a software suite of design tools and agree to purchase a "production quantity" of chips. At this point, the negotiations for the IP core begin.

No characterization numbers were available for the IBM core, so all numbers reflect the Mentor/Inventra predictions for a 0.5 um process.

Important Parameters:

Block Size - The number of bits shifted in and out for each step of the coding. Fixed to 1 for this decoder.
Constraint Length - The number of blocks used for each step of the coding. The complexity of the hardware is, in general, exponential with respect to this value.
Code Wordlength - The number of bits in each code word. Code rate = block size/code wordlength
Modulation Scheme - The modulation scheme assumed for computation of Branch Metrics. Different assumptions about the modulation scheme can have a drastic effect on the complextity of the hardware.
Code bit word length - The number of sampled bits per code bit. This determines the complexity of the branch metric computation hardware.
Truncation Depth - the number algorithm steps to store in memory for traceback. In general, a smaller traceback depth increases the chance that the algorithm will have to force a decision before an optimal answer can be found.
Accumulated State Metric Wordlength - The wordlength of values in the traceback memory

In order for a fair comparison between different Viterbi decoders, all of these parameters should be the same. Mentor characterized the module for an ASIC implementation in a 0.5um CMOS process with the following parameters.

Block size	Constraint Length	Code Wordlength	Modulation Scheme	Code Bit Word Length	Truncation Depth	Accumulated St. Mtr. Wordlength
1	7	2	BPSK (apparently)	3	48	not specified

Because the block allows resource sharing of the ACS (Add/Compare/Select) blocks, the performance and gate count vary with the number of ACS units assumed.

# ACS units 1 8 64

Speed (Msps) 0.810 6.32 85

Gates 3,200 19,400 34,900

Viterbi Decoder
Hantro Products Oy

data sheet

Hantro also offers a parameterizable Viterbi decoder which has the same basic architecture as the Mentor/Inventra core. The ACS units are also assumed to be resource-shared with the Hantro Viterbi-decoder. It has been characterized on an Altera EPF10K10 FPGA with the follow characteristics and results:

Block size	Constraint Length	Code Wordlength	Modulation Scheme	Code Bit Word Length	Truncation Depth	Accumulated St. Mtr. Wordlength
1	7	2	BPSK or QPSK (not specified)	3	55	not specified

No. of ACS units	No. of Logic Cells	Ram Bits	Max Speed
4	500	5120	45 MHz (Msps not available)

In addition to offering HDL source code, Hantro also offers a post-route test bench and test vectors as well as simulation and synthesis scripts. These could reduce design time if they were compatible with the design groups tools.

Ethernet PHY Core
Mysticom

product brief

Mysticom offers an Ethernet PHY core which consists of an analog hard block coupled with a digital soft block. The block is intended for a 0.35 um digital process with 3 metal layers. From my discussions with Debbie Vogt at Mysticom, they negotiate with specific fab houses to get design tools which they use to create a GDSII analog block and a standard cell netlist (w/SDF file) for the digital portion. I'm still waiting for power and area estimates from her, but I'm not sure that they will be forthcomming...

Rhett Davis
wrdavis@eecs.berkeley.edu

# ACS units	1	8	64
Speed (Msps)	0.810	6.32	85
Gates	3,200	19,400	34,900