Approach

• Performance (bits/sec)
• Power (mW/bit)
• Cost ($/unit)
• Design effort (engineer-months)

C54x Description

For our implementation, we choose to use the VC5402, which has the following features:

• Operates at 100 MIPS with a core voltage of 1.8V
• I/O pins operate at 3.3V
• 16K word x 16 bits of dual-access RAM
• 4K word x 16 bits of ROM
• Internal DMA.

Hardware capabilities of the entire C54x series include:

• Three 16-bit data buses and one 16-bit program memory bus
• 40 bit ACC with 40 bit barrel shifter and two independant accumulators
• A single cycle non-pipelined MAC
• Single-instruction repeat and block-repeat operations for program code
• Block-memory-move instructions for better program and data management
• Arithmetic instructions with parallel store and parallel load
• Up to 168K single access RAM
• Up to 32K dual access ram
• Up to 8M word external memory access
• Six channel DMA controller

Viterbi Implementation

 http://www-s.ti.com/sc/psheets/spra071/spra071.pdf

The C54x is highly optimized to perform the Viterbi Decomposition due to the following features of its ALU:

• A single cycle compare, select, and store unit (CSSU) is used to compare branch metrics, record the larger value, and store the appropriate decision bit, all in one cycle
• Dual accumulators allow for dual add/subtract operations to occur in one clock cycle
• The above 2 instructions allow a butterfly to occur in 5 cycles - 1 load local distance, 2 CSSU, 2 dual add/subtract

Specifications for our design include:

• uncoded word length = 1
• coded word length (n) = 2
• constraint length (K aka. L) = 7
• branch metric calculation is QPSK
• this means 4 transitions for each state and 64x4=256 total transitions
• soft decision wordlength (q) = 6
• chain-backing depth (D) = 96
• generator polynomials: p0 = 171, p1= 133 (octal)
• data rate 100 kbs
• goal: bit error rate (BER) = 10^-4
• signal to noise ratio (SNR) degradation 0.05dB

From the TI Appplication Report, we have the following benchmarks for required operations/frame:
(FS = frame size, FR = frame rate)

Metric update: Cycles/frame = (#States/2 butterflies × butterfly calculation + TRN store + local dist calculation.) × # bits
    = (2 K-2 × 5 + 2 K-5 + 1 + n × 2 n-1 ) × FS
Traceback: Cycles/frame = (loop overhead and data storage + loop × 16) × # bits/16
    = (9 + 12 × 16) × FS/16
    = 201 × FS/16
Data reversal: Cycles/frame = 43 × FS/16
Total MIPS = Frame rate × (metric update + traceback + data reversal) cycles/frame
    = FR × [(2 K-2 × 5 + 2 K-5 + 1 + n × 2 n-1 ) × FS + (201/16) × FS + (43/16) × FS]
    = FR × FS × (2 K-2 × 5 + 2 K-5 + 1 + n × 2 n-1 + (201 + 43)/16)
    = FR × FS × (2 K-2 × 5 + 2 K-5 + n × 2 n-1 + 16.25)

So, for a frame size of 100K bits and frame rate of 1 Hz, we require 18.425 MIPS, well below the 100 MIPS provided by our processor.  This allows the processor to perform other operations than just decoding.  Alternatively, the processor can handle up to 582 Kbps performing only decoding, provided that the memory it must access can be loaded quickly enough.

Power:
 

	Voltage	Current	Power
Core CPU	1.8 V	33 mA	59.4 mW
External Pins	3.3 V	30 mA	99 mW
Total Power			158.4 mW
IDLE2  (shut down CPU and peripherals)	2.5 V	2 mA	5 mW
IDLE3  (shut down processor entirely)	2.5 V	.005 mA	0.0125 mA

Note: Power data for the external RAM is not yet available, since TI does not yet list any approved vendors of external DRAM for the C54x series.

Cost:
 

Cost of Chip (50K quantities)	$5 - $75 ea.
Emulator Development Kit	$2,995
Code Composer Development Environment	$3156.45
Simulator	$1578.22
C Compiler/Assembler/Linker	$2367.33
Debugger	$3156.45

Development Tools:

TI boasts a fairly sophisticated, integrated set of development tools.  The Code Composer Development Environment claims to seamlessly integrate the compiler/assembler/linker, debugger, simulator and emulator.  It includes a signal probe, profiler, multiprocessor debugging, data visualization, interactive compiling, and a development environment similar to Microsoft Visual C++.  Run-time libraries are available to speed code development and assure code optimality, and TI claims efficiency of compiled code to be close to hand-assembled code.

Development Time:

This project could be completed in approximately 1 engineer week, from start to finish, using the latest tools.  This is based upon the somewhat sophisticated (comparitively) development tools available for the TI line of DSPs, the availability of run-time libraries, the availability of the Viterbi algorithm application report (with included code snippets), and the availability of configurable emulator boards with JTAG pins.

Code Size:
The code size should be less than 500 lines of assembly, which will easily fit into a ROM with 4K words.

Physical Chip Size:
The 144 pin ball grid array (BGA) measures 12 mm per side (144 mm^2).

Conclusion

This chip is an excellent choice for a low data rate implementation of the Viterbi Decoder.  The chip is fast, low power, and has specialized instructions that greatly accelerate the speed of decoding.  An application report from TI will speed development, and the with less than 20% of the chip operation time being utilized for a 100 Kbit/sec decoder, there is plenty of processing power remaining to implement other blocks in the receiver chain.

References

• VC5402 Datasheet:   http://www-s.ti.com/sc/psheets/sprs079/sprs079.pdf
• TMS320C5000 DSP Family Functional Overview: http://www-s.ti.com/sc/psheets/spru307/spru307.pdf
• Tool Information: http://www.ti.com/sc/docs/dsps/tools/c5000/c54x/
• Pricing Information: Arrow Semiconductor http://www.arrowsemi.com/