Tentative CS 150 Course Outline

Week 1

29 August

Lecture #1: Course Administration [ppt, pdf]
Quick Review: The Many Representations of Hardware
Background Questionaire and Diagnostic Quiz [doc, pdf]

31 August

Lecture #2: Combinational Logic [ppt, pdf]
HW #1 assigned [doc, pdf]

2 September

Lab Lecture #1: EECS 150 Lab Introduction and CAD Tools

Readings: K&B, Ch.1: 1.1-1.4, pp. 1-27; Ch.2: 2.1-2.4, pp. 33-65;

Week 2

5 September

Labor Day

7 September

Lecture #3: Programmable Logic
PLAs/PALs and FPGAs
HW #2 assigned

9 September

Lab Lecture #2: Designing with Verilog
HW #1 due
Lab #1: CAD Tools [doc, pdf]

Readings: K&B, Ch.3: 3.1, pp. 93-103; Ch.4: 4.1-4.3, pp. 156-205;

Week 3

12 September

Lecture #4: Verilog Hardware Description Language

14 September

Lecture #5: Basic Finite State Machines
Flip-Flops, Registers, Shifters, Counters
HW #3 assigned

16 September

Lab Lecture #3: Implementation of FSMs
HW #2 due
Lab #2: Designing with Verilog [doc, pdf]

Readings: K&B, Ch.3: 3.6: pp. 139-146; Ch.6: 6.1, 6.3, pp.259-278, 289-298;

Week 4

19 September

Lecture #6: Moore vs. Mealy Machines

21 September

Lecture #7: Verilog for State Machines
HW #4 assigned (due 7 October)

23 September

Lab Lecture #4: Debugging
HW #3 due
Lab #3: Implementation of FSMs [doc, pdf]

Readings: K&B, Ch.7: 7.1-7.3, pp. 308-339.

Week 5

26 September

Lecture #8: Midterm I Review

28 September

Midterm I

30 September

Lab Lecture #5: Logic Analyzers
Lab #4: Debuggings [doc, pdf]

Week 6

3 October

Lecture #10: FSM Synthesis, State Machine Timing

5 October

Lecture #11: Case Study
SDRAM/Memory Controller
HW #5 assigned

7 October

Lab Lecture #6: Project Checkpoint #1 (one week)
HW #4 due
Lab #5: Logic Analyzers [doc, pdf]

Readings: K&B, Ch.6: 6.2.1, 6.2.2, pp. 279-282; Ch.10: 10.4, pp. 467-482.

Week 7

10 October

Lecture #12: Project Description (Electronic Etch-a-Sketch)

12 October

Lecture #13: Datapath Building Blocks and Interconnection Strategies
Arithmetic Units, Register Files, Shifters, FIFOs, Memories
Point-to-Point, Single Bus, Mixed
HW #6 assigned

14 October

Lab Lecture #7: Project Checkpoint #2 (one week)
HW #5 due
Checkpoint #1: Game Controller Interface

Readings: K&B, Ch.5: 5.5-5.7, pp.234-249; Ch.6: 6.3. pp. 289-295.

Week 8

17 October

Lecture #14: Datapath Control
State Machines for Control, Register Transfer

19 October

Lecture #15: Datapath Control
Microprogrammed State Machines
HW #7 assigned

21 October

Lab Lecture #8 Project Checkpoint #3 (two weeks)
HW #6 due
Checkpoint #2: LCD Interface

Readings: K&B, Ch.9: 9.1-9.4, pp. 401-446 + supplements.

Week 9

24 October

Lecture #16: Control Timing and Retiming

26 October

Lecture #17: Control Parallelism and Pipelining
HW #8 assigned

28 October

Lab Lecture #9: Checkpoint #3 (continued)
HW #7 due
Checkpoint #3 Memory Interface (continued)

Week 10

31 October

Lecture #18: Testing, Fault Models, Design for Test

2 November

Lecture #19: State Machine Optimization
State Encodings, State Assignments, and State Partitioning
HW #9 assigned (due 18 November)

4 November

Lab Lecture #10: Putting the Project Together (three weeks)
HW #8 due
Checkpoint #3 Memory Interface DUE

Readings: K&B, Ch.7: 7.4, pp. 339-346; Ch.8: 8.1-8.3, pp. 356-386.

Week 11

7 November

Lecture #20: Midterm II Review

9 November

Midterm II

11 November

Veterans Day

Week 12

14 November

Lecture #22: State Machines, Signaling, Metastability, Arbiter Design, Hazards

16 November

Lecture #23: Arithmetic Circuits
Basic Building Blocks
HW #10 assigned (due 2 December)

18 November

Lab Lecture #11: Final Project Demonstration, Report, and Grading Details
HW #9 due
Final Project (continued)

Readings: K&B, Readings: K&B, Ch.3: 3.5, pp. 129-139; Ch.6: 6.2.3-6.2.5, pp.282-289.

Week 13

21 November

Lecture #24: Arithmetic Circuits
Combinational and Sequential Multiplier

23 November

Lecture #25: Design Methodology
EARLY PROJECT CHECKOFF

25 November

Thanksgivings
No Lab Lecture

Readings: K&B, Ch.5: 5.8, pp. 249-253; Ch.10: 10.5, pp. 482-487.

Week 14

28 November

Lecture #26: Logic Design with Switches

30 November

Lecture #27: Evolution of FPGA Architecture
STANDARD PROJECT CHECKOFF

2 December

No Lab Lecture
HW #10 due

Week 15

5 December

Lecture #28: Power-Based Design

7 December

Lecture #29: Course Summary and Review

9 December

No Lab Lecture
PROJECT WRITE-UP DUE

Last Updated: 30 August 2005; randy@cs.Berkeley.edu