ASPLOS Wild and Crazy Idea Session '98 Submissions:

Included below are all of the abstracts that were submitted to the ASPLOS Wild and Crazy Idea Session (1998), minus those that authors explicitly requested to be excluded. A cursory attempt has been made to classify these by topic. Other than that, however, there is no particular significance to the order in which abstracts are listed. Note that abstracts have been kept in their original formats. This includes: either PDF (.pdf), Postscript (.ps), or TEXT (.txt).

The Freedom CPU Project:

  • The Fredom CPU architecuture: a GNU/GPL'ed high-performance 64-bit microprocessor developed in an open, Web-wide collaborative environment.
    Andrew Balsa <>

    Here is the current home-page for the Freedom CPU architecture

  • Dynamic Compilation/Evolutionary Architectures:

  • Evolutionary Compilation to Long Instruction Superscalar Microarchitectures for Exploiting Parallelism at All Levels
    Tom Conte <>
    (North Carolina State University)
  • Introspective Computers
    Krisztian Flautner <>, Trever Mudge <>
    (University of Michigan, Ann Arbor)
  • A Good Way to Exploit Predictable Control Flow? Vectorize programs at Runtime!
    Sriram Vajapeyam <>
    (indian Institute of Science, Bangalore)
  • Evolving Operating Systems: the Kernel of the Future
    Ariel Tamches <> and Barton Miller <>
    (Computer Sciences Department, University of Wisconsin, Madison)
  • Esoteric Computation Models or Media

  • Programming Biological Cells
    Ron Weiss <>, George Homsey <>, Radhika Nagpal <>
    (MIT Laboratory For Computer Science)
  • Enantiomers for Molecular Computation and Manufacturing Systems
    Nicholas Weaver <>
    (University of California at Berkeley)
  • Wavenets (Click here for extended whitepaper.)
    John Chapin <>
    (MIT Laboratory for Computer Science)
  • 3D Macro-Cellular Automata Based on Spherical IC Lattices
    Andreas Nowatzyk <>
    (Compaq Western Research Lab)
  • Randomized Computation Networks
    Rick Hangartner <>
    (Tera Computer Corporation)
  • Explotations of ILP

  • Data Threaded Microarchitecture: Dataflow on the Fly
    Dick Wilmot <>
  • Using Critical-Path Length as a Practical Performance Metric or Dataflow Microprocessors
    Bradley Kuszmaul <>
    (Yale University)
  • Scheduled Dataflow Architecture: A Synchronous Execution Paradigm for Dataflow
    Hyong-Shik Kim <> and Krishna Kavi
    (University of Alabama in Huntsville)
  • Procedurally Data-Driven Machines: a Whole New Paradigm.
    Reiner Hartenstein <>
    (Kaiserslautern University)
  • TimeWarp: a Mechanism for Extracting Task-Level Parallelism
    John G. Cleary <>, Richard Littin <>, Murray Pearson <>, J. David McWha <
    (Department of Computer Science, University of Waikato, Hamilton, New Zealand)
  • MLP yes! ILP no!
    Andrew Glew <>
    (Intel Microcomputer Research Labs and Univeristy of Wisconsin, Madison)
  • General Purpose VLIW Processors using Replay Buffers
    Kevin Rudd <>
    (Stanford University)
  • Free Parallel Computer
    Kirilka Nikolova <>
    (University of Electro-Communications, Tokyo)
  • A Proposal for Implementing a SIMD Type
    Jose Alvarez <>
    (University of Michigan, East Lansing)
  • Multiprocessing and Cache Coherence

  • Multiprocessors Should Support Simple Memory Consistency Models
    Mark Hill <>
    (University of Wisconsin, Madison)
  • Space-Time Memory
    U. Ramachandran <>> (Georgia Tech),
    R. Nikhil <>, J.Rehg <, R. Halstead Jr. <>, C. Joerg <>, L. Kontothanassis <>, K. Knobe <>
    (Compaq Cambridge Research Lab)
  • Combining RISC-based SMP's and Loop-Level Parallelism Sets the Standard
    Daniel Pressel <>
    (US Army Research Laboratory, APG MD)
  • Efficiency vs. Peak Performance: A Vote for Efficiency
    Daniel Pressel <>
    (US Army Research Laboratory, APG MD)
  • Vault: A VLSI Architecture Using Lightweight Threads
    Ian Watson <> and Greg Wright <>
    (University of Manchester, England)
  • Reconfigurable Computing

  • High-level Compilation for Reconfigurable Architectures
    Jonathan Babb <>
    (MIT Laboratory for Computer Science)
  • Architectures and Compilers for Tiger Machines
    Seth Goldstein <>
    (Carnegie-Mellon University)
  • RDF: Reconfigurable Data-Flow
    Oskar Mencer <>, Michael Flynn <>, and Martin Morf <>
    (Computer Systems Laboratory, Stanford University)
  • Programmer Support

  • Programming Language Support for Architecture (and Operating System) Innovation
    Tito Autry <> and Sally McKee
    (Oregon Graduate Institute of Science and Technology)
  • The Computer Architect Gets More Choices if the Programmer Gets a More Powerful Computer
    Kay Litchfield <>
    (The Boeing Company)
  • Performance Nonmonotonicity Bugs
    Nate Kushman <> and Volker Strumpen <>
    (MIT Laboratory for Computer Science)
  • Realtime Support

  • A Proposal for a Real-Time Processor Core
    Claudia Mathis <> and Reinhold Weiss
    (Institute for Technical Informatics, Technical University of Graz, Steyrergasse, Austria)
  • Real Time Predictable Caching or (Cache + Memory)/2
    G.N.S. Prasanna <>
    (Lucent Technologies).
    Note: Please contact the author for more details, which have been omitted for patentability reasons.
  • Capabilities and Security

  • Addresssing to Achieve Security (and More)
    J. Leslie Keedy <>
    (University of Ulm, Germany)
  • Intelligent Memory and DRAM modifications

  • Virtualizing Physical Memory
    John Carter <> and the Impulse Group
    (University of Utah)
  • Active-Page Programming: New Paradigms for Using Intelligent Memory
    Frederic Chong <>, Mark Oskin <>, Justin Hensley <>, Aneet Chopra <>, and Lucian Vlad-Lita <>
    (University of California at Davis)
  • Serially Multiported DRAM (SMDRAM) based computer architectures
    D. Litaize <>, A Mzoughi <>, P Sainrat <>, and C. Rochange <>
    (IRIT University, Toulouse France)
  • Intelligent Disks and other I/O

  • The End of Central Processor Units
    David Patterson <> and Kimberly Keeton <>
    (University of California at Berkeley)
  • Active Storage Networks
    David Nagle <> and Greg Ganger <>
    (Carnegie-Mellon University)
  • Disk Delay Lines
    Philip Machanick <>
    (University of the Witwatersrand, South Africa)
  • SPINE: Executing Application Code on I/O Processors
    Marc Fiuczynskki <> and Brian Bershad <>
    (University of Washington)
    Richard Martin <> and David Culler <>
    (University of California at Berkeley)