Real Time Predictable Caching or (Cache + Memory)/2

                 G. N. S. Prasanna, Lucent Technologies

Problem:

Processor   architectures  for   the  real-time DSP/multimedia/control
world,  and the non-real  time RISC/CISC world have traditionally been
quite   distinct.   The lack  of  predictability   of basic  RISC/CISC
hardware-mechanisms, especially    caches,  has   forced     real-time
applications  to  generally preclude their use.   It has  been a major
challenge to devise a memory-heirarchy which is fast, predictable, and
transparent to the programmer.

Solution method:

Techniques,   based  on  integer-linear-programming   (ILP)  have been
recently  developed  (Cinderella from  Princeton  University, etc.) to
predict  the worst-case  execution-time  (WCET)  of programs on  cache
based architectures. We tackle the problem of predictable caching (and
memory-hierarchy  in  general), by  trying  to improve  the WCET.  The
preliminary    results  indicate    significant    changes  in   basic
memory-hierarchy  mechanisms. The early results  from our work suggest
ways  in which the hitherto    incompatible domains of real-time   and
non-real time architectures may merge.