Slide 10 of 46
Notes:
By the year 2010, all predictions (e.g. the SIA/SRC 1997 Technology Roadmap for Silicon) indicate a technical capability to fabricate more than 1B logic gates, or 64 Gbits of memory per chip.
At this time, it is predicted that the overall performance, power dissipation, and reliability of such single-chip systems will be limited by interconnections among devices, and the implications of interconnect (communication) will dominate all aspects of the design process, from fundamental process technology to system-level architecture.
Because of the complexity of such designs,acceptable design productivity is only possible through re-use of existing components and structures on new designs, leading to the concept of System-on-a-Chip (SOC).
However, there is significant evidence that unless the techniques needed to master the integration of these pre-designed blocks of “Intellectual Property” (IP) are developed and made widely available, design costs (design, validation, verification, and test) will limit application developers to writing software for a small number of high-volume standard parts, oriented towards specific classes of (consumer-oriented) applications.
