The following comments, regarding Lecture 4 and Lecture 5, are from Olivet Chou, of Mitsubishi Electronics America, Inc.
3D-RAM(1) P/N M5M410092 0.50um proc, 2metal, 4poly, in production
3D-RAM(2) P/N M5M410092A 0.45um proc, 2metal, 4poly, in production
3D-RAM(3) P/N M5M410092B 0.40um proc, 2metal, 4poly, production soon
The lecture notes incorrectly states the process to be 0.55 um, 1 level metal. The point is Mitsubishi is very much in sync with the state-of- the-art CMOS process technology.
But, the point is totally missed. The sense amps are not suitable to function as the first line cache between the processor (or the on- processor cache) and the DRAM cells because of the speed mismatch between the two is still too significant. Mitsubishi believes the approach of integrated SRAM on a DRAM chip is the best approach to solve this speed mismatch problem, even if there is NO on-chip ALU. Mitsubishi pioneered Cache DRAM (CDRAM) and introduced a Multi-port Cache DRAM (MP-RAM) at the quarterly semiconductor memory supplier meet (JEDEC meeting) at Portland, OR in June 1996. A on-chip SRAM 100% matches up with the controller's appetite for data, while the internal global bus between the DRAM and the on-chip SRAM compensates for the slower speed of the sense amps with an 8x width. Note again that this principle holds even if there is NO on-chip ALU. The first step to a truly intelligent RAM to get this IRAM to provide the RIGHT data to the controller cycle by cycle without missing a beat!
For the latest analysis on CDRAM (or DRAM + SRAM) advantage, please see the July 22, 1996 issue of the EE Times newspaper, p.57.
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