Notes from discussion
January 26, 1996
This unstructured list of issues is a summary of points
brought up by the last two talks.
Can't change basic DRAM technology
Issues based on the noise from logic (potentially a major problem)
Can the processing be internally bit-sliced or interleaved with
Vector ISA vs on-chip caching strategies?
Questions about the management of multiple IRAM chips
How do we utilize the wide bus(es)?