CAD Issues for Multi-Chip Modules
CAD Issues for Multi-Chip Modules
m Design partitioning, considering complex constraints.
Ô Pin limitations, power requirements, performance, cost, MTBF, etc.Ô Long-term tight coupling to chip design technologies (e.g. optimal I/O locations with bumps, use of MCM M1 for chip power distribution)
m Routing of n-layer (4+) MCMs, including power and ground, with complex constraints.
Ô O(600+) pins/chip; 2D I/Os with bumpsÔ Signal reflections & coupling, matched stubs, via location, etc.