Multi-Chip Modules: Design Methodology and CAD Aspects
Evolution of Electronic Design Technology: Early 1980s
Evolution of Electronic Design Technology: Mid 1980s
Evolution of Electronic Design Technology: Late 1980s
System-Level Performance Growth
Impact of I/C Delay on Overall System
IBM Case Study: CPU Cycle Times
MCM Impact on System Performance
Increase in I/O Pin Requirements
Package Penalties: Excess Interconnect Area
The Future of First-Level Packaging: Déja Vu?
Feature Size Trends for ICs and Boards
Typical MCM Product Positioning
Cost Implications of Process Flow
Integrated Subsystem Business Model
CAD Issues for Multi-Chip Modules
CAD Issues for Multi-Chip Modules
Previous approach: lumped RLC method
Previous approach: Convolution
Convolution: Quadratic Time Complexity
Lumped RLC method: spurious responses
Execution Time vs Simulation Length
Cell Replication to Improve Network Partitions
Cell Replication to Improve Network Partitions
Cell Replication to Reduce Delay