ASIC (Power, Cost)

• Power:

  • Gated clocks (adds to design time)
  • Supply voltage: 1.0 V
  • Power: 483uW
  • Energy/Frame: 22.2 uJ
  • Minimal static power (100 transistors tied to clock line): 5.3 uW

• Cost:

  • Total chip area: 24.9mm^2

Previous slide

Next slide

Back to first slide

View graphic version