CS258 Spring '08: Final List Of Papers

Reading 1:
Wednesday
1/30

• The Future of Wires, Ron Ho, Kenneth W. Mai, and Mark A. Horowitz. Appears in Proceedings of the IEEE, Vol 89, No. 4, April 2001
  
• An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes, Daniel H. Linder and Jim C. Harden, Appears in IEEE Transactions on Computers, Vol. 40, No. 1, January 1991

Additional Reading:

• Mesochronous clocking and communication in on-chip networks, Daniel Wiklund
  
• Low-Latency Plesiochronous Data Retiming, Larry R. Dennison, William J. Dally, Duke Xanthopoulos,  Advanced Research in VLSI, 1995. Proceedings., Sixteenth Conference on 27-29 March 1995

Reading 2:
Monday
2/4

• Performance Analysis of k-ary n-cube Interconnection Networks, Bill Dally, Appears in IEEE Transactions on Computers, Vol. 39, No 6, July 1990
• Virtual-channel Flow Control, Bill Dally, Appears in IEEE Transactions on Parallel and Distributed Systems, Vol 3, No 2, March 1992

Reading 3:
Wednesday
2/6

• A Delay Model and Speculative Architecture for Pipelined Routers, Li-Shiuan Peh and William J. Dally,  In Proceedings of the 7th International Symposium on High-Performance Computer Architecture (ICS 2001), Jan. 22-24, 2001
• Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks, John Kim, William J. Dally, and Dennis Abts. In Proceedings of the International Symposium on Computer Architecture (ISCA 2007), June 2007

• Design Tradeoffs for Tiled CMP On-Chip Networks, James Balfour and William Dally. Appears in Proceedings of the International Conference on Supercomputing (ICS) 2006
• Express Virtual Channels: Towards the Ideal Interconnection Fabric, Amit Kumary, Li-Shiuan Pehy, Partha Kunduz and Niraj K. Jhay. Appears in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2007

• Architecture of a message-driven processor.  W. J. Dally,  L. Chao,  A. Chien,  S. Hassoun, W. Horwat,  J. Kaplan,  P. Song,  B. Totty, and  S. Wills.  Proceedings of the 14th Annual International Conference on Computer Architecture. ISCA 1987. See ISCA Retrospective
• Exploiting Two-Case Delivery for Fast Protected Messaging.  Kenneth Mackenzie, John Kubiatowicz, Anant Agarwal, and Frans Kaashoek. Proceedings of 4th Int'l Symposium on High Performance Computer Architecture Feb. 1998.

• Active messages: a mechanism for integrated communication and computation  Thorsten von Eicken, David E. Culler, Seth Copen Goldstein,     Klaus Erik Schauser. Appears in the Proceedings of the 19th annual international symposium on Computer architecture, 1992. See ISCA Retrospective
• Supporting systolic and memory communication in iWarp, Shekhar Borkar, Robert Cohn, George Cox, Thomas Gross, H. T. Kung, Monica Lam, Margie Levine, Brian Moore, Wire  Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon Webb. In Proceedings of the 17th Annual International Symposium on Computer Architecture (ISCA), 1990.
• The Message-Driven Processor: A Multicomputer Processing Node with Efficient Mechanisms, William Dally, J.A. Stuart Fiske, John Keen, Richard Lethin, Michael Noakes, Peter Nuth, Roy Davison, and Gregory Fyler, Appears in IEEE Micro, April 1992.

• LogP: Towards a Realistic Model of Parallel Computation, David Culler, Richard Karpy, David Patterson, Abhijit Sahay, Klaus Erik Schauser, Eunice Santos, Ramesh Subramonian, and Thorsten von Eicken.  In Proceedings of PPOPP, May 1993
• Scalar Operand Networks: On-chip Interconnect for ILP in Partitioned Architectures, Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal, Proceedings of the International Symposium on High Performance Computer Architecture, February 2003

Supplemental reading:

1. Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams, Michael Bedford Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, and Anant Agarwal. Proceedings of International Symposium on Computer Architecture, June 2004

• Area-Performance Trade-offs in Tiled Dataflow Architectures, Steve Swanson, Andrew Putnam, Martha Mercaldi, Ken Michelson,Andrew Petersen, Andrew Schwerin, Mark Oskin, and Susan Eggers, Appears in International Symposium on Computer Architecture (ISCA) 2006.
  • The WaveScalar website is: http://wavescalar.cs.washington.edu/
    
• The Distributed Microarchitecture of the TRIPS Prototype Processor, K. Sankaralingam, R. Nagarajan, P. Gratz, R. Desikan, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, W. Yoder, R. McDonald, S.W. Keckler, and D.C. Burger, 39th International Symposium on Microarchitecture (MICRO), December, 2006.
  • The TRIPS website is: http://www.cs.utexas.edu/~trips/

• Synergistic processing in Cell's multicore architecture, M. Gschwind, P. Hofstee, B. Flachs, M. Hopkins, Y. Watanabe, T. Yamazaki. Appears in IEEE Micro, March-April 2006
• Analysis and Performance Results of a Molecular Modeling Application on Merrimac, Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. Dally, Eric Darve.  Appears in Proceedings of the 2004 ACM/IEEE Converence on Supercomputing, November 2004
• WaveScalar,  Steve Swanson, Ken Michelson, Andrew Schwerin and Mark Oskin. Appears in 36th Annual International Symposium on Microarchitecture (MICRO-36), December 2003

• Weak Ordering - A New Definition, S.V. Adve and M.D. Hill, Proceedings of the 17th Annual International Symposium on Computer Architecture, May 1990. See ISCA Retrospective
• Memory Consistency and Event Ordering in Scalable Shared-Memory  Multiprocessors, Kourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip Gibbons, Anoop Gupta, and  John Hennessy,  Proceedings of the International symposium on Computer Architecture, 1990. See ISCA Retrospective

• Is SC + ILP = RC?  Chris Gniady, Babak Falsafi, T. N. Vijaykumar, In Proceedings of the 26th annual international symposium on Computer architecture, 1999

• Daniel Lenoski, James Laudon, Truman Joe, David Nakahira, Luis Stevens, Anoop Gupta, and John Hennessy, The DASH Prototype: Implementation and Performance, Proceedings of the International symposium on Computer Architecture, 1992. See ISCA Retrospective
• Anant Agarwal, Richard Simoni, John Hennessy, and Mark Horowitz, An Evaluation of Directory Schemes for Cache Coherence, Proceedings of the International symposium on Computer Architecture, 1988.  See ISCA Retrospective

• Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model, James Archibald and Jean-Loup Baer, ACM Transactions on Computer Systems, Vol. 4, No. 4, November 1986,
  
• LimitLess Directories: A Scalable Cache Coherence Scheme, David Chaiken, John Kubiatowicz, and Anant Agarwal, Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS IV), pages 224-234, April 1991.

• DDM - A Cache-only Memory Architecture. E. Hagersten, A. Landin, and S. Haridi. Appears in IEEE Computer, September 1992
• Comparative performance evaluation of cache-coherent NUMA and COMA architectures, Per Stenström, Truman Joe, and Anoop Gupta.  In  Proceedings of the 19th annual international symposium on Computer architecture, 1992.

• The Stanford FLASH multiprocessor,  J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D.  Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, J. Hennessy.  In Proceedings of the 21st Annual International Symposium on Computer Architecture (ISCA) 1994.
• An adaptive cache coherence protocol optimized for migratory sharing, Per Stenström, Mats Brorsson, Lars Sandberg, In Proceedings of the 20th Annual International Symposium on Computer Architecture (ISCA) 1993

• ReVive: cost-effective architectural support for rollback recovery in shared-memory multiprocessors, Milos Prvulovic, Zheng Zhang, Josep Torrellas, In Proceedings of the 29th annual international symposium on Computer architecture (ISCA) May 2002
• SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery, Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood, In Proceedings of the 29th annual international symposium on Computer architecture (ISCA) May 2002

• Closing the window of vulnerability in multiphase memory transactions, John Kubiatowicz, David Chaiken, Anant Agarwal. In Proceedings of the fifth international conference on Architectural support for programming languages and operating systems (ASPLOS) 1992.
• Timestamp snooping: an approach for extending SMPs,   Milo M. K. Martin, David A. Wood, Daniel J. Sorin, Anatassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, and Mark D. Hill, In Proceedings of the Ninth international conference on Architectural support for programming languages and operating systems, 2000

Supplemental Reading (For Anant Agarwal's Talk):

• On-Chip Interconnection Architecture of the Tile Processor, David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal, In IEEE Micro, September-October 2007
• TILE64TM Processor: A 64-Core SoC with Mesh Interconnect,   Shane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce,Vince Leung, John MacKay, Mike Reif, Liewei Bao, John Brown, Matthew Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay Stickney, John Zook, In Proceedings of ISSCC, 2008

• Transactional memory: architectural support for lock-free data structures, Maurice Herlihy. J. Eliot B. Moss, Proceedings of the 20th annual international symposium on Computer architecture, 1993
• Efficient synchronization: let them eat QOLB, Alain Kägi, Doug Burger, James R. Goodman, Proceedings of the 24th annual international symposium on Computer architecture, 1997

Reading 19:
Monday
4/21

• Synchronization without Contention, John M. Mellor-Crummey and Michael L. Scott.  In Proceedings of The 4th International Conference on Architectural Support for Programming Languages and Operating Systems, pages (ASPLOS), 1991
  
• Reactive synchronization algorithms for multiprocessors, Beng-Hong Lim and Anant Agarwal. In proceedings of the sixth international conference on Architectural support for programming languages and operating systems (ASPLOS), 1994

Reading 20:
Wednesday
4/23

• Language Support for Lightweight Transactions, Tim Harris and Keir Fraser. In proceedings of the International Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA), 2003
• Transactional Memory Coherence and Consistency. Lance Hammond, Vicky Wong, Mike Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, and Kunle Olukotun. In proceedings of the International Symposium on Computer Architecture (ISCA), 2004

• Unbounded Transactional Memory. C. Scott, Ananian Krste, Asanovi´c Bradley, C. Kuszmaul, Charles E. Leiserson, and Sean Lie. In Proceedings of the International Symposium on Computer Architecture (ISCA), 2005
• Virtualizing Transactional Memory. Ravi Rajwar, Maurice Herlihy, and Konrad Lai. In Proceedings of the International Symposium on Computer Architecture (ISCA), 2005

• LogTM: Log-based Transactional Memory.  Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill & David A. Wood.  Appears in the proceedings of the 12th Annual International Symposium on High Performance Computer Architecture (HPCA-12), 2006
  
• An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees. Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Bronson, Jared Casper,Christos Kozyrakis, Kunle Olukotun. In Proceedings of the International Symposium on Computer Architecture (ISCA), 2007

• The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism,  M. Franklin and G. S. Sohi. In Proceedings 19th International Symposium on Computer Architecture (ISCA-19), 1992.
• Data Speculation Support for a Chip Multiprocessor. Lance Hammond, Mark Willey, and Kunle Olukotun. In Proceedings of the 8th ACM Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 1998.

• Comparing Memory Systems for Chip Multiprocessors. Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahain, Mark Horowitz, Christos Kozyrakis. Proceedings of the International Symposium on Computer Architecture (ISCA), 2007
• The Sensitivity of Communication Mechanisms to Bandwidth and Latency.  Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren, John D. Kubiatowicz, and Anant Agarwal.  Proceedings of 4th Int'l Symposium on High Performance Computer Architecture (HPCA), Las Vegas, NV, Feb 1-4, 1998.