University
of California, Berkeley. Electrical Engineering and Computer
Sciences The Donald O. Pederson Center for Electronic Systems Design Software: Software Homepages: |
Wife: Ruth Brayton, RN
Children: Jane, James, Michael
Father In Law of : Daniel Burchard, Debbie Marr.
Grandchildren: Tommy and Lia Burchard,
Matthew, Mason, and Mariella Brayton.
Pets: Tiffy (cat), Toby (dog)
1. Logic Synthesis
and Verification (homepage - offered Spring 2002 by A. Kuehlmann at
2. Logic Synthesis
for Hardware Systems (homepage - offered Spring 2000 by Brayton at
3. NTU TV logic course (DS 763CA) description and homepage
4. next generation logic synthesis (course announcement)
5.
The
unknown component problem
6. Sequential Synthesis and verification
1. A Theory of Non-Deterministic Networks (invited
talk -Workshop on Boolean Problems, Sept., 2002 in
2. Optimization of Multi-Level Multi-Valued Networks (invited
talk - ISMVL, May., 2002 in
1. Observability Relations for Multi-Output Nodes
2. Combinational Test Generation Using Satisfiability
3. Valid Clock Frequencies and Their Computation in Wavepipelined Circuits
4. Multi-Valued Optimization on Post Logic Networks
5. Topologically Constrained Logic Synthesis
6. Whirlpool PLAs: A Regular Logic Structure and Their Synthesis
7. Reducing Multi-Valued Algebraic Operations to Binary
8. A Theory of Non-Deterministic Networks
1.
"A
Theory of Nonlinear Networks" (with J.K. Moser), Quarterly of Applied
Mathematics , April, 1964.
2.
"Latin
Squares of All Orders n Not Equal to 2,3,6" (with A.J. Hoffman, D.
Coppersmith) IBM Research Report RC-4532 and Bull. of AMS , Vol. 80, No.
1, Jan. 1974 and as “Self-orthogonal
Latin Squares," Colloquia Internazionalle sulle TEORIE COMBINATORIE,
September 3-15, 1973; Academia Nazionale Dei Lincei, Roma, pp. 509-517, 1976.
3.
"Yield
Maximization and Worst-Case Design with Arbitrary Statistical
Distributions," (with S.W. Director and G.D. Hachtel), IEEE Transactions
on Circuits and Systems, CAS-26, September 1979.
4.
"Stability
of Dynamical Systems: A Constructive Approach," (with C. H. Tong) IEEE
Transactions on Circuits and Systems, CAS-26, pp. 224-234, April 1979
5.
"The
Sparse Tableau Approach to Network Analysis and Design", (with G. D.
Hachtel and F. G. Gustavson), The World of Large Scale Systems , IEEE
Press, 1982.
6.
"The
Decomposition and Factorization of Boolean Expressions" (with C.
McMullen), ISCAS Proceedings, April 1982.
7.
“A
Comparison of Logic Minimization Strategies Using ESPRESSO: An APL Program
Package for Partitioned Logic Minimization”, (with G.D. Hachtel, L.
Hemanchandra, R. Newton and A. Sangiovanni- Vincentelli), Proceedings of the
International Symposium on Circuits and Systems, pp. 42-48, Rome, Italy, April
1982
8.
"Logic
operations are properties of computer-simulated interactions between excitable
dendritic spines" (with G. Shepherd), Neuroscience , 1987 Apr,
21(1):151-65.
9.
"The
Yorktown Silicon Compiler" (with R. Camposano, G. De Micheli, R. H. J. M.
Otten, and J. van Eijnhoven), Silicon Compilation, ed. D. D. Gajski, Addison-Wesley,
1988.
Office: 573 Cory Hall
Phone: (510) 643-9801 Fax:
(510) 642-2739
Email: brayton@eecs.berkeley.edu