Low Power Wireless EEG

• Designing wireless EEG for TMS-EEG-fMRI system [NIH R01MH127104]
• Designed & tested µV precision ADC for SCµM-V (single-chip micro mote) with Intel 16 FinFET Process
• Built prototype with off-shelf ADC (ADS1299) and SCµM via serial peripheral interface (SPI)
• Spring 2023 Tapeout Class; Fall 2023 Bringup Class

65nm Tapeout Shuttle Top-Level Integration

• BSAC point of contact of 65nm tapeout shuttle between TSMC
• Integrated chip top-level for research groups – Prof. Liwei Lin’s lab, Prof. Jun-Chau Chien’s lab and Prof. Kris Pister’s lab

Inclinometer for Microrobotic Platforms

• Designed dual-axis accelerometer-based inclinometer for sub-cm hexapod in a single mask silicon process
• Achieved 0.8m degree resolution, over 13-degree range, and less than 1% angular error

DAC-driven Transimpedance Amplifier

• Designed fully differential 300Ω-loaded transimpedance amplifier with TSMC 28nm CMOS process
• Achieved 250Ω gain, 70dB loop gain, 9.77-bit ENOB, 700MHz BW, 4.98mW power, 4.95ns settling, and 53.7µV output noise, with 1V supply and 50µA reference current
• Stabilized CMFB between class AB output stage and folded-cascode first stage

38-mm Smartwatch Liquid-Crystal Display Driver

• Drove 272×340 pixels, with 1.4V light-to-dark full swing transition, sequentially at 60Hz refresh rate
• Built 2-stage op-amp with GDPK 45nm CMOS process, 1.8V and 1V power supplies, telescopic-cascode, class AB amplifier, Miller compensation, and single biasing current source

RISC-V CPU Processor

• Implemented RISC-V ISA with 3-stage pipelined CPU, cache memory, and control status register (CSR)
• Designed configurable direct-mapped and 2-way set associative cache with write-back and -through policies
• Front-end Verilog design and simulation, and back-end synthesis and PAR with ASAP7 7nm process

Terahertz (THz) None-line-of-sight (NLOS) Imaging

Prof. Shang-Hua Yang, Yang Research Group, EE, NTHU

• Submitted proposal to Ministry of Science and Technology (MOST), Taiwan
• Asynchronous optical sampling (ASOPS) Terahertz time-domain spectroscopy (THz-TDS) system

IC Lab QR Code Decoder

• Decoded rotated 25×25 QR code within 64×64 random-background bitmap images into URL web address
• Ranked A and won second-place in synthesis contest (over half of classmates are graduate students) (performance index (PI) is defined as the product of total area, timing constrain, and total simulation cycles)

ASCII and utf-8 Files Encoding

• Achieved 70% fewer storage space for utf-8 text files with Huffman encoding scheme

MOS Fabrication

• Fabricated MOS from silicon wafer in Tsing Hua Lab (Class 1000, The Federal Standard 209E), highest-class cleanroom in Taiwan’s academia
• Characterized MOS with carrier mobility and threshold voltage through two-probe measurement

Terahertz Curvature Sensing System

• Undergraduate Project Oral and Poster Presentation Competition (rank 1/53), EE, NTHU
• Characterized surface roughness based on THz continuous wave scattering

Full-Custom Eight Frequency Mode Clock Generator

• Built full-custom eight frequency mode clock divider with 0.18um CMOS process, with three-bit half-adders, double-edged-triggered flip-flops, and True Single Phase Clock (TSPC)
• Achieved maximum operating frequency of 530MHz, at TT (25ºC) corner, with 1.91mW power
• Won the performance competition with the smallest layout area consumption

Logic Design Puzzle Tetris Game

• Established Tetris and innovative jigsaw puzzle in Verilog HDL with Xilinx Vivado on FPGA board
• Integrated with counter, timer, keyboard, speaker, LCD, and LED