Research

48 V to Point-of-Load Vertical Power Delivery for Next-Generation Ultra-High-Power Microprocessors

High-performance microprocessors (e.g., GPUs, CPUs, ASICs, etc.) serve as the engine of data center computing platforms and the foundation for technical progress in areas such as artificial intelligence, deep learning, autonomous vehicles, and numerous other applications. In recent years, the electric power consumption of microprocessors has increased dramatically and is approaching 1000 W due to the fast-growing demand for greater computational power.

As power levels increase, the 48-V bus architecture is gradually replacing the legacy 12-V dc bus in modern data centers since the power distribution losses (\(i^2R\) losses) decrease by sixteen-fold with the quadrupling of the bus voltage. This makes the design of the voltage regulation modules (VRMs) responsible for the 48 V to point-of-load (PoL) power conversion more challenging with a quadrupled voltage conversion burden. In particular, the continued increase in power levels with maintained or even reduced space for power conversion leads to an ever-increasing demand for higher power density. Moreover, higher power conversion efficiency is required for easier thermal management and reduced electricity consumption of data centers.

The main challenges of 48-V-to-PoL power conversion include: i) high conversion ratio, ii) high output current, iii) high efficiency, iv) high power density, and v) fast transient response.

I'm addressing these challenges through innovative converter topologies, multi-phase coupled magnetics, and advanced packaging techniques. Specifically, I'm exploring extreme-performance hybrid switched-capacitor (SC) converters that can leverage both the greatly superior energy density of capacitors (100-1000x compared to inductors and transformers) and the fast dynamic response and current ripple reduction enabled by coupled inductors. With high power densities, these converters can be placed directly underneath the microprocessors for vertical power delivery (VPD) to significantly reduce the power distribution network (PDN) losses and open up the topside area on the motherboard for high-speed communication, compared to today's lateral power delivery (LPD) architecture.

Select publications: [Zhu COMPEL’23, Zhu APEC’23, Zhu APEC’22, Zhu ECCE’21]

Modeling and Control of Pure and Resonant Switched-Capacitor Converters

Modeling and analysis

In pre-existing analytical models of pure and resonant switched-capacitor (SC) converters, the input and output capacitances (\(C_{\mathrm{in}}\) and \(C_{\mathrm{out}}\)) have long been assumed to be infinitely large so that the input and output can be modeled as ideal voltage sources. However, in practice, the terminal capacitances can be insufficient to ensure ideal input and output behaviors due to space and cost constraints. This work reveals that finite terminal capacitances can have considerable effects on the output impedance (\(R_{\mathrm{out}}\)) and overall efficiency of SC converters.

Select publications: [Zhu TPEL’23, Zhu COMPEL’21a, Zhu APEC’21]

Control

This work proposes a multi-resonant compensation control (MRCC) technique for resonant switched-capacitor (ReSC) converters that can adaptively compensate for the negative effects of finite terminal capacitances by ensuring multi-resonant and full zero current switching (ZCS) operation with adjusted duty ratio and switching frequency, demonstrating a more than 5x terminal capacitance reduction without harming the overall efficiency compared to the conventional control technique.

Select publication: [Zhu COMPEL’21b]

Discrete State Event-Driven (DSED) Simulation of Power Electronics Systems

Power electronic systems are intrinsically hybrid dynamical systems composed of continuous states and discrete events. Continuous states are typically state variables that depict the system's behavior, such as capacitor voltages and inductor currents. In contrast, discrete events, such as switching events of semiconductor switches, can change instantaneously and lead to the system's transition from one operating mode to another. This hybrid nature makes it challenging to simulate power electronic systems efficiently with high numerical accuracy. This work proposes a discrete state event-driven (DSED) framework for the offline simulation of such hybrid dynamical systems. Two key elements of the proposed DSED framework are: 1) an adaptive numerical algorithm for flexible integration of continuous states and 2) an event-driven mechanism for efficient locating of discrete events. The proposed DSED simulation framework is applied to a 50-kVA solid-state transformer (SST) and a multileg full-bridge Class-D power amplifier to verify its accuracy and efficiency by comparisons with experimental waveforms and simulated waveforms of Simulink and PLECS. Up to 100-fold and 10-fold improvements in simulation speed are achieved at the same level of numerical accuracy compared with Simulink and PLECS, respectively.

The commercial simulation software DSIM is developed based on this work.

Select publications: [Zhu TPEL’19, Zhao MPEL’20, Shi TIE’21, Yu TPEL’21]