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Wk |
Date |
Lecture / Reading |
Homework / Quiz |
Lab / Project |
| 1 | Tu 1/16 | Lecture #1: Course Administration [ppt,
pdfx2,
pdfx6] Quick Review: The Many Representations of Hardware |
HW #1 Assigned [doc,
pdf] Due 1/26 at 2:10 PM Background Form and Quiz #0 Solution [pdf] |
Lab Lecture #1: EECS 150 Lab
Introduction and FPGA CAD Tools [ppt, pdfx2, pdfx6] |
| Th 1/18 | Lecture #2: Combinational Logic [ppt,
pdfx2,
pdfx6]
Readings: K&B, Ch.1: 1.1-1.4, pp. 1-27; Ch.2: 2.1-2.4, pp. 33-65; Ch.3: 3.1, pp. 93-103; |
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| 2 | Tu 1/23 | Lecture #3: Programmable Logic [ppt. pdfx2, pdfx6] PLAs/PALs and FPGAs |
HW #2 Assigned [doc, pdf] Due 2/2 at 2:10 PM HW #1 Due 1/26 Solution [doc, pdf] |
|
| Th 1/25 | Lecture #4: Verilog Hardware
Description Language [ppt, pdfx2, pdfx6] Readings: K&B, Ch.3: 3.6: pp. 139-146; Ch.4: 4.1-4.3, pp. 156-205; |
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| 3 | Tu 1/30 | Lecture #5: Basic Finite State Machines Flip-Flops, Registers, Shifters, Counters [ppt, pdfx2, pdfx6] |
HW #3 Assigned [doc, pdf] Due 2/9 at 2:10PM HW #2 Due Solution [doc, pdf] |
Lab Lecture #3: Verilog Synthesis and FSMs [ppt, pdf] Lab #2: Designing with Verilog [doc, pdf, zip] Solutions: [zip] |
| Th 2/1 | Lecture #6: Moore vs. Mealy Machines
[ppt, pdfx2,pdfx6] Readings: K&B, Ch.6: 6.1, 6.3, pp.259-278, 289-298; Ch.7: 7.1-7.3, pp. 308-339; |
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| 4 | Tu 2/6 | Lecture #7: Verilog for State Machines [ppt, pdfx2, pdfx6] |
HW #4 Assigned [doc, pdf] Due: 2/23 at 2:10 PM HW #3 Due Solution [doc, pdf] |
Lab Lecture #4: Debugging and Verification [ppt, pdf] Lab #3: Implementation of FSMs [doc, pdf, zip] |
| Th 2/8 | Lecture #8: FSM Synthesis, State Machine Timing [ppt, pdfx2, pdfx6] Readings: K&B, Ch.6: 6.2.1, 6.2.2, pp. 279-282; Ch.8: 8.4, pp. 386-392; |
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| 5 | Tu 2/13 | Lecture #9: Midterm I Review |
Lab Lecture #5: Logic Analyzers [ppt,pdf] Lab #4: Debugging and Verification [doc, pdf, zip] |
|
| Th 2/15 | Midterm I: Solution [zip] | |||
| 6 | Tu 2/20 | Lecture #10: Case Study SDRAM/Memory Controller [ppt, pdfx2, pdfx6] |
HW #5 Assigned [doc, pdf] Due: 3/2 at 2:10 PM HW #4 Due Solution [doc, pdf] |
Lab Lecture #6: Project Checkpoint #0 Basic SDRAM Subsystem [pdf, pdf] (one week) Lab #5: Logic Analyzers [doc, pdf, zip] |
| Th 2/22 | Lecture #11: Project Description (Video Conferencing System) [ppt, pdfx2, pdfx6] Readings: K&B, Ch.10: 10.4, pp. 467-482. |
|||
| 7 | Tu 2/27 | Lecture #12: Datapath Building Blocks Arithmetic Units, Register Files, Shifters, FIFOs, Memories [ppt, pdfx2, pdfx6] |
HW #6 Assigned [doc, pdf] Due: 3/9 at 2:10 PM HW #5 Due Solution [doc, pdf] |
Lab Lecture #7: Project Checkpoint #1 (Part I) Video Capture and Display (Part 1)[ppt, pdf] (two weeks) Checkpoint #0: Basic SDRAM Subsystem [zip, pdf, doc] Solution [bit] |
| Th 3/1 | Lecture #13: Datapath Interconnection Strategies Point-to-Point, Single Bus, Mixed [ppt, pdfx2, pdfx6] Readings: K&B, Ch.5: 5.5-5.7, pp. 234-249; Ch.6: 6.3. pp. 289-295. CLD Chapter 11 [html]. |
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| 8 | Tu 3/6 | Lecture #14: Datapath Control State Machines for Control, Register Transfer [ppt, pdfx2, pdfx6] |
HW #7 Assigned [doc, pdf] Due: 3/16 at 2:10 PM HW #6 Due Solution [doc, pdf] |
Lab Lecture #8: Project Checkpoint #1 (Part II) [ppt, pdf] Checkpoint #1: Video Capture to Display System [doc, pdf, zip] |
| Th 3/8 | Lecture #15: Datapath Control Microprogrammed State Machines [ppt, pdfx2, pdfx6] Readings: K&B, Ch.9: 9.1-9.4, pp. 401-446. CLD Chapter 12 [html] |
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| 9 | Tu 3/13 | Lecture #16: Control Timing and Retiming [ppt, pdfx2, pdfx6] |
HW #8 Assigned [doc, pdf] Due: 4/6 at 2:10 PM HW #7 Due Solution [doc, pdf] |
Lab Lecture #9: Project Checkpoint #2 Compression/Decompression (One Week) [ppt, pdf] Checkpoint #1 Video Capture and Display (continued) [doc, pdf, zip] Solution [bit] |
| Th 3/15 | Lecture #17: Control Parallelism and Pipelining [ppt, pdfx2, pdfx6] |
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| 10 | Tu 3/20 | Lecture #18: Midterm II Review [ppt, pdfx2, pdfx6] |
Lab Lecture #10: Checkpoint 3 One Way Conferencing System (Part I)
[ppt, pdf]
Checkpoint #2: Compression/Decompression [doc, pdf] |
|
| Th 3/22 | Midterm II Solution [jpg] |
|||
| 3/26-3/30 | Spring Break | |||
| 11 | Tu 4/3 | Lecture #20: Testing, Fault Models, Design for Test [ppt, pdfx2, pdfx6] |
HW #9 Assigned [doc, pdf] Due: 4/13 at 2:10 PM HW #8 Due Solution [doc, pdf] |
Lab Lecture #11: Checkpoint 3 Part II [ppt, pdf] Checkpoint #3: One-Way Conferencing System (Part 1) Solution [bit] |
| Th 4/5 | Lecture #21: State Machine Optimization State Encodings, State Assignments, and State Partitioning [ppt, pdfx2, pdfx6] Readings: K&B, Ch.7: 7.4, pp. 339-346; Ch.8: 8.1-8.3, pp. 356-386. |
|||
| 12 | Tu 4/10 | Lecture #22: State Machines, Signaling,
Metastability, Arbiter Design, Hazards [ppt, pdfx2, pdfx6] |
HW #10 Assigned [doc, pdf] Due: 4/20 at 2:10 PM HW #9 Due Solution [doc, pdf] |
Lab Lecture #12: Checkpoint 4 and Putting The Project Together:
Two-Way Video Conferencing System [ppt, pdf] Checkpoint #3: One-Way Conferencing System (Part 2) Early Project Checkoff |
| Th 4/12 | Lecture #23: Arithmetic Circuits Basic Building Blocks [ppt, pdfx2, pdfx6] Readings: K&B, Ch.3: 3.5, pp. 129-139; Ch.6: 6.2.3-6.2.5, pp.282-289. |
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| 13 | Tu 4/17 | Lecture #24: Arithmetic Circuits Combinational and Sequential Multiplier [ppt, pdfx2, pdfx6] |
HW #10 Due Solution [doc, pdf] |
Lab Lecture #13: Final Report Specification
[ppt, pdf] Checkpoint #4: Two-Way Conferencing System [doc, pdf] Standard Project Checkoff |
| Th 4/19 | Lecture #25: Design Methodology [ppt, pdfx2, pdfx6] Readings: K&B, Ch.5: 5.8, pp. 249-253; Ch.10: 10.5, pp. 482-487. |
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| 14 | Tu 4/24 | Lecture #26: Logic Design with Switches [ppt, pdfx2, pdfx6] |
No Lab Lecture Project Report Due |
|
| Th 4/26 | Lecture #27: Evolution of FPGA Architecture [ppt, pdfx2, pdfx6] | |||
| 15 | Tu 5/1 | Lecture #28: Power-Based Design [ppt, pdfx2, pdfx6] |
No Lab Lecture |
|
| Th 5/3 | Lecture #29: Course Summary and Review [ppt, pdfx2, pdfx6] |
| UC Berkeley | http://www-inst.eecs.berkeley.edu/~cs150/ | EECS 150 Spring 2007 |
