Computer Science 150: Components and Design Techniques for Digital Systems (5 Units)

Catalog Description

CS 150. Components and Design Techniques for Digital Systems. (5) Three hours of lecture, one hour of discussion, and three hours of laboratory per week. Prerequisites: 61C, Electrical Engineering 40 or 42. Basic building blocks and design methods to contruct synchronous digital systems. Alternative representations for digital systems. Bipolar TTL vs. MOS implementation technologies. Standard logic (SSI, MSI) vs. programmable logic (PLD, PGA). Finite state machine design. Digital computer building blocks as case studies. Introduction to computer-aided design software. Formal hardware laboratories and substantial design project. Informal software laboratory periodically throughout semester. (F,SP) Katz, Newton, Pister.

Course Goals

• Understand digital logic at the gate and switch level including both combinational and sequential logic elements.
• Understand clocking methodologies to manage information flow and preservation of circuit state.
• Appreciate digital logic specification methods and the compilation process that transforms these into logic networks.
• Gain experience with computer-aided design tools for implementation with programmable logic devices.
• Appreciate the advantages/disadvantages between hardware and software implementations of a function.

Course Times and Locations

Lecture: M, W 1:00-2:30, 306 Soda

Lab Lecture: F 2:00-3:00, 125 Cory

Discussions: Th 3:00-4:00, Th 4:00-5:00, F 9:00-10:00, F 11:00-12:00 (Note change from 10-11!);
ALL DISCUSSIONS MEET IN 125 CORY! You may attend any discussion section.

Laboratories: Tu 9:00-12:00, Tu 5:00-8:00, W 9:00-12:00, W 5:00-8:00, all in 125 Cory.

Course Textbook

R. H. Katz, G. Borriello, Contemporary Logic Design, 2^nd Ed., Pearson Prentice-Hall, Upper Saddle River, NJ, 2005.

Contemporary Logic Design, Second Edition

Tentative Course Schedule

Course Grading

• Homeworks: 10%
• In-class Quizzes: 5%
• Laboratories (Labs 1-5): 15%
• Midterms (2): 20%
• Final Project (including project Checkpoints 1, 2, 3): 30%
• Final Exam: 20%

Course Instructor

Professor Randy H. Katz, Computer Science Division, EECS Department, 637 Soda Hall, 510-642-8778.

Office Hours: M 3-4 PM, W 12-1 PM. E-mail: randy@cs.Berkeley.edu

Teaching Assistants

Bryan Brady, bbrady@eecs.berkeley.edu

Jay Chen, jayzchen@berkeley.edu

Po-kai Chen, pokai@berkeley.edu, Head TA

Brian Gawalt, gawalt@eecs.berkeley.edu

Jack Tzeng, tze_jack@berkeley.edu

Readers

David Lin, dtlin@berkeley.edu

Kevin Lin, klin84@berkeley.edu

Homework and Examination Regrade Policies

• Assignments are distributed on Wednesday, collected the Friday of the following week at 2 PM (before Lab Lecture).
• Expect a short quiz on the week’s homework at the start of the Wednesday’s lecture for the week that the homework is due. This is to motivate you to start on it early and to come to lecture on a regular basis! It is worth 5% of your final grade.
• Submit assignments to CS150 homework box next to 125 Cory. 
• Homework is graded on effort, not correctness. Homeworks are worth 10% of your final grade.
• See calendar on this web page for homework handouts.
• Please attend a discussion section to hear about the solutions to the exams. This will usually take place during the week following the return of the exam.
• Regrades are by written petition only, and in general, we are very stingy with regrades. The petition should succinctly state why you believe that your solution is correct when we believed it to be wrong. These should be given to the instructor within one week of the return of the exam and following the discussion section in which the solutions are presented. Regrades are considered in batch, to insure consistency.

Public Discussion

• Post/receive announcements, questions, and discussion
• UseNet news group:  ucb.class.cs150
• student e-mail list:  eecs150@eecs.berkeley.edu (please use judiciously!)

Technical Documentation

To be filled in.