Agenda
Agenda
9:00 Introduction (RN)
9:30 Design Verification (RN)
10:15 Implementation Verification (RN)
10:30 BREAK
11:00 Implementation Verification (cont.) (RN)
11:30 Manufacture Verification (KK)
12:30 LUNCH
1:30 Synthesis for Testability - Combinational (KK)
2:30 Synthesis for Testability - Sequential (SD)
3:00 BREAK
3:30 Synthesis for Testability - Sequential (cont.) (SD)
5:00 FINISH