New Trends in Testing and Verification

Richard Newton

University of California

New Trends in Testing and Verification

Agenda

Verification Tasks

Common Representations Used in the Design Process

Specification vs. Description

Connectivity Verification Systems (CVS)

Simplified Levels for Verification

Verification Tasks

Common Representations Used in the Design Process

Design Specification and Verification

The Role of VHDL in System Design Verification

Behavior and Structure

Behavior and Structure: Two Faces of the Same Coin

An Interpretation of Behavior & Structure

Logic Simulation

Why Can't we Make Simulators Faster?

Compiled Simulation

Logic Simulation

Inertial vs. Transport Delay Models

Why not Synthesis-Directed Simulation?

Example Finite-State Machine with Encoded States

Example Finite-State Machine Next-State Logic

Multilevel Next-State Logic

Conventional Logic Simulator

Optimal Variable Packing

"Synthesized for Simulation"

Synthesis-Directed High-Level Simulation

Timing Verification

Switch-Level Timing Verification

Electrical Simulation

Electrical Simulation Issues

Mixed-Level Simulation

Use of Multiprocessors

Summary

Verification Tasks

Classification of Implementation Verification Approaches

Formal Specification of Behavior

Higher-Order Logic

Higher-Order Logic

The Software Analogy: Abstract Datatype Approach to Consistency

The Lambda System [Fourman, et. al. 88]

The Lambda System

Cubes and Minterms

Prime and Irredundant Networks

Role of Don't-Cares in Logic Synthesis

Role of Don't-Cares in Logic Synthesis

Role of Don't-Cares in Logic Synthesis

Optimality & Redundancy in Combinational Logic

Testability and Logic Synthesis

Test Generation for Finite-State Machines

Combinational Logic Verification: Exhaustive Simulation

Symbolic Simulation

Combinational Logic Verification: Flattening

Combinational Logic Verification: Use Testing Techniques

Combinational Logic Verification

Path-Oriented DEcision Making [Goel, 1981]

Combinational Logic Verification: Multi-level Tautology

Symbolic Verification

Combinational Logic Verification: Binary Decision Diagrams

Use of BDDs for Verification

Use of BDDs for Verification

Use of BDDs for Verification

Use of BDDs for Verification

Combinational Verification Using Canonical Form

Connectivity Verification

Connectivity Verification

Finite-State Machines

Finite-State Machines

Sequential Verification Across Different Levels

Sequential Verification Across Different Levels [Devadas 1987]

Exploiting "Don't Care" Information

Verification at the Logic Level

Difficulties in Sequential Verification at the Logic Level

Verification via Symbolic Simulation

Enumeration of State Transition Graph

Illustration of Dynamic Enumeration of the STG

Example of Dynamic Enumeration

Example of Dynamic Enumeration

Cube Enumeration and Simulation

Cover Extraction

State-of-the-Art for Sequential Verification

State-of-the-Art for Sequential Verification

Summary