State-of-the-Art for Sequential Verification
State-of-the-Art for Sequential Verification
name
cse
sse
sand
planet
sbc
sbc.1
scf
tlc
mclc
sbc.2
sbc.3
inp
7
7
11
7
33
16
27
3
11
31
27
out
7
7
9
19
24
1
54
5
6
13
17
gates
192
130
555
606
473
172
959
76
148
475
492
latch
4
6
6
6
6
7
8
10
11
13
17
valid
states
16
13
32
48
54
65
115
400
35
2,040
2,764
edges
in STG
141
58
183
142
19,308
1,782
274
2,000
917
2,474,094
1,451,108
CPU Time
[Devadas 87]
2.0 s
0.6 s
8.6 s
6.8 s
250 m
21.2 s
23.6 s
22.6 s
23.4 s
22.6 h
5.4 h
* times for VAX 8800 Ultrix