New Trends in Testing and Verification
Common Representations Used in the Design Process
Connectivity Verification Systems (CVS)
Simplified Levels for Verification
Common Representations Used in the Design Process
Design Specification and Verification
The Role of VHDL in System Design Verification
Behavior and Structure: Two Faces of the Same Coin
An Interpretation of Behavior & Structure
Why Can't we Make Simulators Faster?
Inertial vs. Transport Delay Models
Why not Synthesis-Directed Simulation?
Example Finite-State Machine with Encoded States
Example Finite-State Machine Next-State Logic
Synthesis-Directed High-Level Simulation
Switch-Level Timing Verification
Classification of Implementation Verification Approaches
Formal Specification of Behavior
The Software Analogy: Abstract Datatype Approach to Consistency
The Lambda System [Fourman, et. al. 88]
Prime and Irredundant Networks
Role of Don't-Cares in Logic Synthesis
Role of Don't-Cares in Logic Synthesis
Role of Don't-Cares in Logic Synthesis
Optimality & Redundancy in Combinational Logic
Testability and Logic Synthesis
Test Generation for Finite-State Machines
Combinational Logic Verification: Exhaustive Simulation
Combinational Logic Verification: Flattening
Combinational Logic Verification: Use Testing Techniques
Combinational Logic Verification
Path-Oriented DEcision Making [Goel, 1981]
Combinational Logic Verification: Multi-level Tautology
Combinational Logic Verification: Binary Decision Diagrams
Combinational Verification Using Canonical Form
Sequential Verification Across Different Levels
Sequential Verification Across Different Levels [Devadas 1987]
Exploiting "Don't Care" Information
Verification at the Logic Level
Difficulties in Sequential Verification at the Logic Level
Verification via Symbolic Simulation
Enumeration of State Transition Graph
Illustration of Dynamic Enumeration of the STG
Example of Dynamic Enumeration
Example of Dynamic Enumeration
Cube Enumeration and Simulation
State-of-the-Art for Sequential Verification
State-of-the-Art for Sequential Verification