Summary
Summary
m Simulation is, and will remain, essential for design verification.
Ô The gap between system complexity and simulator performance is widening rapidly, especially for logic and behavioral levels.Ô Synthesis-directed compilers for behavioral and logic simulation will improve performance by more than an order of magnitude.Ô A practical VHDL "policy-of-use" must be determined soon and should be driven by industry (users and CAD vendors; possibly via MCC).Ô General-purpose, massively-parallel machines will offer cost-effective help in the future.Ô Plan for the "simulator of the year" phenomenon.