The Role of VHDL in System Design Verification
The Role of VHDL in System Design Verification
- Very good for certain forms of simulation, especially event-driven logic simulation.
- Severely restrictive, by itself, for general-purpose synthesis or formal verification.
Remember:
Ô A subset of a language is a different language
Ô A sequential language has sequential semantics
e.g. if (Clk'QUIET for 4) .....
if (Clk'STABLE for 4) ....No synchronizing elements in data-flow or netlist views.Compiled-mode simulation not well defined.
- VHDL Policy-of-Use should be driven by synthesis/design needs and then implemented efficiently in simulators. This approach would take full advantage of the power of VHDL.