Sequential Control-Flow Model
Sequential Control-Flow Model
- Based on Von Neumann "fetch;execute;store" with single (serial control flow) or synchronized multiple (parallel control flow) thread(s) of control.
- Proposes an ordering of computation based on strict, temporal sequencing of operations, in line with above cycle.
- Not well suited to the description of hardware since arbitrary hardware rarely fits such a model of computation.
- Ability to combine several operations and treat them as a unit, or block (begin-end, parbegin-parend, ...)
- Ability to allow an operation to be executed in a loop.
- e.g. ISP, DDL/P(1973), Adlib/Sable(1980), AHPL(1973), SLANG(1982).
for(i=0 to 9) {
x[i]=y[i]+c;/* "forall" */
}
j=0; while(j <10){
x[j]=y[j]+c;
j=j+1;
}
VLSI ‘91, Edinburgh