High-Level What?

Narration

Common Representations Used in the Design Process

Sequential Control-Flow Model

Connectivity Verification Systems (CVS)

Converting Procedural Descriptionsto a Dataflow-Oriented Representation

Complications to Dataflow Analysis*

Complications to Dataflow Analysis

Complications to Dataflow Analysis

Narration

Narration

Ella: A Hardware Design & Description Language

Ella: A Hardware Design & Description Language

Representing the Synthesis Problem:The Conventional Approach

Representing the Synthesis Problem:An Alternative Approach

Languages versus Models:A Software Analogy

Behavior and Structure:Two Faces of the Same Coin

Behavior and Structure

Behavior and Structure

Implementing Any Digital FunctionUsing a Single NAND Gate

Abstract Datatype Approach to Consistency:A Software Analogy

An Alternate View of Synthesis

An Alternate View of Synthesis

An Alternate View of Synthesis

An Alternate View of Synthesis

An Alternate View of Synthesis

Two Approaches to Combinational andSequential Optimization

An Alternate View of Synthesis:Implications

Narration

What is High-Level Synthesis?

What is an Architecture?

What is an Architecture?

What is an Architecture?

Specification vs. Description

High-Level Synthesis

Conventional Steps inHigh-Level Synthesis

Parallelism, Pipelining,and Graph Folding

Maximally ParallelandMaximally Pipelined

Maximally Parallel, Minimum Control States

Widthwise Folding via Symbolic Dependencies

Parallelism, Pipelining, and Graph Folding

Maximally Pipelined: Storage Requirements

Sharing Storage

Approaches to Scheduling

As-Soon-As-Possible (ASAP) andAs-Late-As-Possible (ALAP) Scheduling

Narration

State and Statements

State and Statements

State Counter Generation

State and Statements

Data and Control

“Simulator-of-The-Year” Phenomenon

“Simulator-of-The-Year” Phenomenon

PP Presentation

VHDL: The “nroff/latex” of Design

3-Bit Parity Function: "Control-Oriented"

3-Bit Parity Function: "Dataflow-Oriented"

3-bit Parity Function:Possible VHDL Implementation

Role of VHDL

"I synthesize from C" or"I synthesize from VHDL"

Components of Our Approach to Behaviorwith Priorities

Representing Time for Behavioral Description

Why Should Time be Discrete?

Representing Time for Behavioral Descriptions

Encoding Information in Time & Space

Narration

Formal Methods for Design Representation

Formal Methods for Design Representation

Formal Methods for Design Representation

The Synchronous VHDL Subset

Results

Assume a Semantic Approach

Approach

Method of Formal Semantics

Reactions are State Transitions

Semantics S defines aOne-Level Time

Microsemantics Sd defines aTwo-level Time

Observe Three Levelsof Time in VHDL

Problem Statement

Properties of a SemanticsHuizing and Gerth,“Semantics of Reactive Systems in Abstract Time,” June 1991

Origin of the Properties

The RMC Barrier[HG91]

Limits on Microsemantics

An Implementation Strategy

Experience

Hardware-Software Codesign

Narration