3-bit Parity Function: Possible VHDL Implementation
3-bit Parity Function: Possible VHDL Implementation
ENTITY parityFunction IS
PORT( A, B, C : IN t_wlogic; parity : OUT t_wlogic )
END parityFunction;
ARCHITECTURE full OF parityFunction IS
BEGIN
PROCESS (A, B, C)VARIABLE count : integer;BEGINcount := 0;IF A = '1' THEN count := count +1; END IF;IF B = '1' THEN count := count +1; END IF;IF C = '1' THEN count := count +1; END IF;IF (count MOD 2) = 0 THENELSEEND IF;
END PROCESS;
END full;
m If VHDL is the “nroff” of design description; we want WYSIWYG design entry!