Chapter Review
• Transition from Simple Gates to more complex gate building blocks
• Conversion from AND/OR, OR/AND to NAND/NAND, NOR/NOR
• Multi-Level Logic: Reduced gate count, fan-ins, but increased delay
• Use of misII to optimize multi-level logic and to perform mappings
• Time Response in Combinational Logic:
Gate Delay, Rise Time, Fall Time
Hazards and Hazard-free Design