A Revolution in Test in the Late 1990s?
??Can Synthesize a Guaranteed Fully-Testable, Non-Scan Implementation of Any Collection of FSMs.
??Almost always requires fewer gates or less area than full scan.
??Almost always requires shorter tester times (in many cases by one or two orders of magnitude) than full scan.
??Can handle faults in embedded machines, machines with feedback, etc. - any topology of interconnected machines.
??Test patterns generated as a by-product of the synthesis, so synthesis time represents a saving of ATPG time.