Write Serialization for Coherence
Writes that appear on the bus (BusRdX) are ordered by bus
- performed in writer’s cache before other transactions, so ordered same w.r.t. all processors (incl. writer)
- Read misses also ordered wrt these
Write that don’t appear on the bus:
- P issues BusRdX B.
- further mem operations on B until next transaction are from P
- read and write hits
- these are in program order
- for read or write from another processor
- separated by intervening bus transaction