Hierarchy Issues

1. Encoding, reencoding, and redundant latch removal (paper by Ashar et al ICCAD'96)
2. FSM decomposition
3. Approximate state space traversal
4. Fast retiming and Ciesielski's factoring - paper by Ciesielski et al
   
5. State of the art equivalence checking - for combinational, sequential, and when retiming is done
6. "Logic Optimization of Design Containing Black Boxes" paper by Aziz and Singhal on hierarchical equivalence checking with application to logic optimization and synthesis of core based designs
7. Hierarchical timing computations

An updated and more detailed list of possible topics and associated papers can be found at
http://www-cad.EECS.Berkeley.EDU/HomePages/brayton/courses/nexsis/outline/outline.html

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