Krste Asanović, Publications by Type

These online copies are provided for your personal research use only.

• Publications organized by year

• Patents
• Journal Publications
• Conference Publications
• Book Chapters
• Technical Reports and Memos
• Theses Supervised

PhD Thesis

• Krste Asanović, "Vector Microprocessors", University of California, Berkeley, May 1998. The thesis is also available as Technical Report UCB/CSD-98-1014, Computer Science Division, University of California, Berkeley.

Patents

• Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanović, "System and method for performing memory operations in a computing system", US Patent 7,398,359, issued July 2008. PDF.
  Continuation patents: US Patent 7,925,839 issued April 2011, PDF, and US Patent 8,321,634 issued November 2012, PDF.

• Krste Asanović and Emmett Witchel, "System and technique for fine-grained computer memory protection", US Patent 7,287,140, issued October 2007. PDF

• Krste Asanović, "A vector processing system with multi-operation run-time reconfigurable pipelines", US Patent 5,805,875, issued September 1998. PDF

Journal Publications

• Colin Schmidt, John Wright, Zhongkai Wang, Eric Chang, Albert Ou, Woorham Bae, Sean Huang, Vladimir Milovanović, Anita Flynn, Brian Richards, Krste Asanović, Elad Alon, and Borivoje Nikolić, "An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET", IEEE Journal of Solid-State Circuits 57(1), January 2022. PDF

• David Biancolin, Albert Magyar, Sagar Karandikar, Alon Amid, Borivoje Nikolić, Jonathan Bachrach, and Krste Asanović, "Accessible, FPGA Resource-Optimized Simulation of Multi-Clock Systems in FireSim", IEEE Micro 41(4), July/August 2021. PDF

• Tae Jun Ham, David Bruns-Smith, Brendan Sweeney, Yejin Lee, Seong Hoon Seo, U Gyeong Song, Young H. Oh, Krste Asanović, Jae W. Lee, and Lisa Wu Wills, "Accelerating Genomic Data Analytics With Composable Hardware Acceleration Framework", IEEE Micro 41(3), May/June 2021. PDF
  Special Issue: Top Picks from Computer Architecture Conferences

• John Wright, Colin Schmidt, Ben Keller, Palmer Dabbelt, Jaehwa Kwak, Vignesh Iyer, Nandish Mehta, Pi-Feng Chiu, Stevo Bailey, Krste Asanović, and Borivoje Nikolić, "A Dual-Core RISC-V Vector Processor with On-Chip Fine-Grain Power Management in 28nm FD-SOI", IEEE Transactions on VLSI Systems 28(12), December 2020. PDF

• David Kohlbrenner, Shweta Shinde, Dayeol Lee, Krste Asanović, and Dawn Song, "Building Open Trusted Execution Environments", IEEE Security & Privacy 18(5), September/October 2020. PDF

• Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Wright, Jerry Zhao, Yakun Sophia Shao, Krste Asanović, and Borivoje Nikolić, "Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs", IEEE Micro 40(4), July/August 2020. PDF

• Colin Schmidt, Alon Amid, John Wright, Ben Keller, Howard Mao, Keertana Settaluri, Jarno Salomaa, Jerry Zhao, Albert Ou, Krste Asanović, and Borivoje Nikolić, "Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28nm FD-SOI", IEEE Solid-State Circuits Letters, 3, July 2020.

• Alon Amid, Kiseok Kwon, Amir Gholami, Bichen Wu, Krste Asanović, and Kurt Keutzer, "Co-Design of Deep Neural Nets and Neural Net Accelerators for Embedded Vision Applications", IBM Journal of Research and Development, November/December 2019. PDF

• Martin Maas, Krste Asanović, and John Kubiatowicz, "A Hardware Accelerator for Tracing Garbage Collection", IEEE Micro 39(3), May/June 2019.
  Special Issue: Top Picks from Computer Architecture Conferences.

• Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, "FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud", IEEE Micro 39(3), May/June 2019.
  Special Issue: Top Picks from Computer Architecture Conferences.

• Christopher Celio, Pi-Feng Chiu, Krste Asanović, Borivoje Nikolić, and David Patterson, "BROOM: An Open-Source Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28nm CMOS", IEEE Micro 39(2), March/April 2019.

• Pi-Feng Chiu, Christopher Celio, Krste Asanović, Borivoje Nikolić, and David Patterson, "Cache Resiliency Techniques for a Low-Voltage RISC-V Out-of-Order Processor in 28-nm CMOS", IEEE Solid-State Circuits Letters, 1(12), December 2018

• Brian Zimmer, Pi-Feng Chiu, Borivoje Nikolić, and Krste Asanović, "Reprogrammable Redundancy for SRAM-Based Cache Vmin Reduction in a 28nm RISC-V Processor", IEEE Journal of Solid-State Circuits, October 2017.

• Ben Keller, Martin Cochet, Brian Zimmer, Jaehwa Kwak, Alberto Puggelli, Yunsup Lee, Milovan Blagojević, Stevo Bailey, Pi-Feng Chiu, Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanović, and Borivoje Nikolić, "A RISC-V processor SoC with integrated power management at sub-microsecond timescales in 28nm FD-SOI", IEEE Journal of Solid-State Circuits, July 2017.

• Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ružica Jevtić, Ben Keller, Stevo Bailey, Milovan Blagojević, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avižienis, Andrew Waterman, Brian Richards, Phillippe Flatresse, Elad Alon, Krste Asanović, and Borivoje Nikolić, "A RISC-V vector processor with simultaneous-switching switched-capacitor DC-DC converters in 28nm FDSOI", IEEE Journal of Solid-State Circuits, 51(4), April 2016.

• Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ružica Jevtić, Stevo Bailey, Milovan Blagojević, Pi-Feng Chiu, Rimas Avižienis, Brian Richards, Jonathan Bachrach, David Patterson, Elad Alon, Borivoje Nikolić, Krste Asanović, "An Agile Approach to Building RISC-V Microprocessors", IEEE Micro 36(2), March/April 2016.

• Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael S. Georgas, Andrew S. Waterman, Jeffrey M. Shainline, Rimas R. Avižienis, Sen Lin, Benjamin R. Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry M. Cook, Albert J. Ou, Jonathan C. Leu, Yu-Hsin Chen, Krste Asanović, Rajeev J. Ram, Miloš A. Popović and Vladimir M. Stojanović, "Single-chip microprocessor that communicates directly using light", Nature 528, pp534-538, December 24, 2015.

• Ruzica Jevtić, Hanh-Phuc Le, Milovan Blagojević, Stevo Bailey, Krste Asanović, Elad Alon, and Borivoje Nikolić, "Per-Core DVFS with Switched-Capacitor Converters for Energy Efficiency in Manycore Processors", IEEE Transactions on VLSI Systems, 23(4), April 2015.

• Scott Beamer, Krste Asanović, and David Patterson, "Direction-Optimizing Breadth-First Search", Scientific Programming, Special Issue: Selected papers from Supercomputing 2012, 21(3-4):137-148, December 2013.

• Yunsup Lee, Rimas Avižienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, and Krste Asanović, "Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators", ACM Transactions on Computer Systems, 31(3), August 2013. ACM DL

• Brian Zimmer, Seng Oon Toh, Huy Vo, Yunsup Lee, Olivier Thomas, Krste Asanović, and Borivoje Nikolić, "SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS", IEEE Transactions on Circuits and Systems-II, 59(12), December 2012. PDF

• Jae W. Lee, Man Cheuk Ng, and Krste Asanović, "Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks", Journal of Parallel and Distributed Computing, 72(11), November 2012. PDF

• Christopher Batten, Ajay Joshi, Vladimir Stojanović, and Krste Asanović, "Designing Chip-Level Nanophotonic Interconnection Networks", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, June 2012. PDF

• Krste Asanović, Rastislav Bodik, James Demmel, Tony Keaveny, Kurt Keutzer, John Kubiatowicz, Nelson Morgan, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel, and Katherine Yelick, "A View of the Parallel Computing Landscape", Communications of the ACM, October 2009. PDF

• John Shalf, Krste Asanović, David A. Patterson, Kurt Keutzer, Tim Mattson, and Katherine Yelick, "The Manycore Revolution: Will the HPC Community Lead or Follow?", SciDAC Review, Fall 2009. PDF

• Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Miloš Popović, Hanqing Li, Henry Smith, Judy Hoyt, Franz Kärtner, Rajeev Ram, Vladimir Stojanović, and Krste Asanović, "Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics", IEEE Micro 29(4), July/August 2009. PDF

• Ronny Krashinsky, Christopher Batten, and Krste Asanović, "Implementing the Scale Vector-Thread Processor", ACM Transactions on Design Automation of Electronic Systems (TODAES), 13(3), 41:1-41:24, July 2008. PDF

• Seongmoo Heo, Ronny Krashinsky, and Krste Asanović, "Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy", IEEE Transactions on VLSI Systems, 15(9), September 2007. PDF
  

• John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos Kozyrakis, James C. Hoe, Derek Chiou, and Krste Asanović, "RAMP: Research Accelerator for Multiple Processors", IEEE Micro 27(2), March/April 2007. PDF
  

• Kenneth C. Barr and Krste Asanović, "Energy-Aware Lossless Data Compression", ACM Transactions on Computer Systems, 24(3):250-291, August 2006.

• C. Scott Ananian, Krste Asanović, Bradley C. Kuszmaul, Charles E. Leiserson, and Sean Lie, "Unbounded Transactional Memory", IEEE Micro 26(1), January/February 2006.
  Special Issue: Top Picks from Computer Architecture Conferences PDF
  

• Jessica Tseng and Krste Asanović, "A Speculative Control Scheme for an Energy-Efficient Banked Register File", IEEE Transactions on Computers, 54(6):741-751, June 2005. PDF

• Ronny Krashinsky, Christopher Batten, Mark Hampton, Steven Gerding, Brian Pharris, Jared Casper, and Krste Asanović, "The Vector-Thread Architecture", IEEE Micro 24(6), November/December 2004.
  Special Issue: Top Picks from Computer Architecture Conferences PDF
  

• Christoforos Kozyrakis, Stylianos Perissakis, David A. Patterson, Thomas Anderson, Krste Asanović, Neal Cardwell, Richard Fromm, Jason Golbus, Ben Gribstad, Kimberly Keeton, Randi Thomas, Noah Treuhaft, and Kathy Yelick, "Scalable processors in the billion-transistor era: IRAM", IEEE Computer, September 1997. PDF

• John Wawrzynek, Krste Asanović, Brian Kingsbury, James Beck, David Johnson, Nelson Morgan, "Spert-II: A vector microprocessor system", IEEE Computer, 29(3):79-86, March 1996. PDF.

• Krste Asanović, James Beck, Jerry Feldman, Nelson Morgan, John Wawrzynek, "Designing a Connectionist Network Supercomputer", International Journal of Neural Systems, December 1993. PDF

• Krste Asanović, Nelson Morgan, John Wawrzynek, "Using Simulations of Reduced Precision Arithmetic to Design a Neuro-Microprocessor", Journal of VLSI Signal Processing, 6:33-44, June 1993.

• John Wawrzynek, Krste Asanović, Nelson Morgan, "The Design of a Neuro-Microprocessor", IEEE Transactions on Neural Networks, 4(3), May 1993. PDF

Conference Publications

2023

• Seah Kim, Jerry Zhao, Krste Asanović, Borivoje Nikolić, and Sophia Shao, "AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads", 56th IEEE/ACM International Symposium on Microarchitecture (MICRO-2023), Toronto, Canada, October 2023.
  Selected as one of IEEE Micro's "Top Picks from Computer Architecture Conferences, 2023".

• Abraham Gonzalez, Aasheesh Kolli, Samira Khan, Sihang Liu, Vidushi Dadu, Sagar Karandikar, Jichuan Chang, Krste Asanović, and Parthasarathy Ranganathan, "Profiling Hyperscale Big Data Processing", 50th ACM/IEEE International Symposium on Computer Architecture (ISCA-2023), Orlando, FL, June 2023.

• Sagar Karandikar, Aniruddha N. Udipi, Junsun Choi, Joonho Whangbo, Jerry Zhao, Svilen Kanev, Edwin Lim, Jyrki Alakuijala, Vrishab Madduri, Yakun Sophia Shao, Borivoje Nikolić, Krste Asanović, and Parthasarathy Ranganathan, "CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems", 50th ACM/IEEE International Symposium on Computer Architecture (ISCA-2023), Orlando, FL, June 2023.

• Jerry Zhao, Seah Kim, Borivoje Nikolić, Krste Asanović, and Yakun Sophia Shao, "An Open-Source Framework for Virtualized and Disaggregated RISC-V Accelerators", Open-Source Computer Architecture Workshop (OSCAR-2023) at the 50th ACM/IEEE International Symposium on Computer Architecture (ISCA-2023), Orlando, FL, June 2023.

• Tianrui Wei, Shangyin Tan, Koushik Sen, Krste Asanović, "Nerv: Probabilistic Dynamic Partial Order Reduction for Hardware", Programming Languages for Architecture Workshop (PLARCH-2023) at the 44th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI-2023), Orlando, FL, June 2023.

• Tianrui Wei, Jerry Zhao, Krste Asanović, "NFC: Next-Generation Formal Verification for High-Performance Caches", Programming Languages for Architecture Workshop (PLARCH-2023) at the 44th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI-2023), Orlando, FL, June 2023.

• Seah Kim, Hasan Genc, Vadim Vadimovich Nikiforov, Krste Asanović, Borivoje Nikolić, and Yakun Sophia Shao, "MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks", 29th International Symposium on High-Performance Computer Architecture (HPCA-2023), Montreal, QC, Canada, February 2023.

2022

• Dayeol Lee, Kevin Cheang, Alexander Thomas, Catherine Lu, Pranav Gaddamadugu, Anjo Vahldiek-Oberwagner, Mona Vij, Dawn Song, Sanjit A. Seshia, and Krste Asanović, "Cerberus: A Formal Approach to Secure and Efficient Enclave Memory Sharing", ACM SIGSAC Conference on Computer and Communications Security (CCS-2022), Los Angeles, CA, November 2022. ACM DL

• Alon Amid, Hasan Genc, Jerry Zhao, Krste Asanović, Yakun Sophia Shao, and Borivoje Nikolić,"Accelerating General-Purpose Linear Algebra on DNN Accelerators", 1st Workshop on Democratizing Domain-Specific Accelerators (WDDSA-2022) at the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO-2022), Chicago, Illinois, October 2022.

• Jerry Zhao, Animesh Agrawal, Borivoje Nikolić, and Krste Asanović, "Constellation: An Open-Source SoC-Capable NoC Generator", 15th International Workshop on Network-on-Chip Architectures (NoCArc-22) at the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO-2022), Chicago, Illinois, October 2022.
  Winner, Best Paper Award

• Harrison Liew, Daniel Grubb, John Wright, Colin Schmidt, Nayiri Krzysztofowicz, Adam Izraelevicz, Edward Wang, Krste Asanović, Jonathan Bachrach, and Borivoje Nikolić, "Hammer: A Modular and Reusable Physical Design Flow Tool", Design Automation Conference (DAC-2022), San Francisco, CA, July 2022.

• Hasan Genc, Seah Kim, Vadim Vadimovich Nikiforov, Simon Zirui Guo, Borivoje Nikolić, Krste Asanović and Yakun Sophia Shao, "Gemmini: An Open-Source, Full-System DNN Accelerator Design and Evaluation Platform", Open-Source Computer Architecture Research Workshop (OSCAR-2022) at the 49th ACM/IEEE International Symposium on Computer Architecture (ISCA-2022), New York City, NY, June 2022.

• Sagar Karandikar, Nayiri Krzysztofowicz, David Biancolin, James Dunn, John Fang, Abraham Gonzalez, Daniel Grubb, Harrison Liew, Albert Ou, Nathan Pemberton, Tim Snyder, Jerry Zhao, Yakun Sophia Shao, Borivoje Nikolić and Krste Asanović, "Chipyard, FireSim, and Hammer: A Push-Button End-to-End Stack for Open-Source Computer Architecture Research", Open-Source Computer Architecture Research Workshop (OSCAR-2022) at the 49th ACM/IEEE International Symposium on Computer Architecture (ISCA-2022), New York City, NY, June 2022.

• Seah Kim, Hasan Genc, Vadim Vadimovich Nikiforov, Krste Asanović, Borivoje Nikolić, Sophia Shao, "Memory-centric, Adaptive Execution for Multi-Tenant DNNs", 2nd Architecture, Compiler, and System Support for Multi-model DNN Workloads Workshop (ACSMD-2022) at the 49th ACM/IEEE International Symposium on Computer Architecture (ISCA-2022), New York City, NY, June 2022.

2021

• Hasan Genc, Seah Kim, Alon Amid, Ameer Haj-Ali, Vighnesh Iyer, Pranav Prakash, Jerry Zhao, Daniel Grubb, Harrison Liew, Howard Mao, Albert Ou, Colin Schmidt, Samuel Steffl, John Wright, Ion Stoica, Jonathan Ragan-Kelley, Krste Asanović, Borivoje Nikolić, and Yakun Sophia Shao, "Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration", Design Automation Conference (DAC-2021), San Francisco, CA, December 2021.
  Winner, Best Paper Award

• Sagar Karandikar, Christopher Leary, Christopher Kennelly, Jerry Zhao, Dinesh Parimi, Borivoje Nikolić, Krste Asanović, and Parthasarathy Ranganathan, "A Hardware Accelerator for Protocol Buffers", 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-54), Athens, Greece, October 2021.
  Honorable Mention in IEEE Micro's "Top Picks from Computer Architecture Conferences, 2021"
  Winner, Distinguished Artifact Award

• Abraham Gonzalez, Jerry Zhao, Ben Korpan, Hasan Genc, Colin Schmidt, John Wright, Ayan Biswas, Alon Amid, Farhana Sheikh, Anton Sorokin, Sirisha Kale, Mani Yalamanchi, Ramya Yarlagadda, Mark Flannigan, Larry Abramowitz, Elad Alon, Yakun Sophia Shao, Krste Asanović, and Borivoje Nikolić, "A 16mm² 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET", IEEE 47th European Solid-State Circuits Conference (ESSCIRC-2021), September 2021.

• Alon Amid, Albert Ou, Krste Asanović, Yakun Sophia Shao, and Borivoje Nikolić, "Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs", IEEE International Symposium on Circuits and Systems, Daegu, Korea, May 2021.

• Jerry Zhao, Abraham Gonzalez, Alon Amid, Sagar Karandikar, and Krste Asanović, "COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2021), March 2021.

• Colin Schmidt, John Wright, Zhongkai Wang, Eric Chang, Albert Ou, Woorham Bae, Sean Huang, Anita Flynn, Brian Richards, Krste Asanović, Borivoje Nikolić, and Elad Alon, "An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET", IEEE International Solid-State Circuits Conference, February 2021.

2020

• Kevin Cheang, Cameron Rasmussen, Dayeol Lee, David Kohlbrenner, Krste Asanović and Sanjit Seshia, "Verifying RISC-V Physical Memory Protection", First International Workshop on Secure RISC-V Architecture Design Exploration (SECRISC-V'20) at the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-20), Boston, MA, August 2020. PDF

• Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Wright, Jerry Zhao, Jonathan Bachrach, Yakun Sophia Shao, Borivoje Nikolić, and Krste Asanović, "Chipyard - Integrated SoC Research and Implementation Environment", Design Automation Conference (DAC-2020), San Francisco, CA, July 2020.
  Invited paper.

• Bin Li, Yipeng Wang, Ren Wang, Charlie Tai, Ravi Iyer, Zhu Zhou, Andrew Herdrich, Tong Zhang, Ameer Haj-Ali, Ion Stoica, and Krste Asanović, "RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization", 6th IEEE International Conference on Network Softwarization (NetSoft-2020), Ghent, Belgium, June/July 2020.
  Winner, Best Paper Award

• Tae Jun Ham, David Bruns-Smith, Brendan Sweeney, Yejin Lee, Seong Hoon Seo, U Gyeong Song, Young H. Oh, Krste Asanovic, Jae W. Lee, Lisa Wu Wills, "Genesis: A Hardware Acceleration Framework for Genomic Data Analysis", 47th ACM/IEEE International Symposium on Computer Architecture (ISCA-2020), June 2020.
  Selected as one of IEEE Micro's "Top Picks from Computer Architecture Conferences, 2020".

• Jerry Zhao, Ben Korpan, Abraham Gonzalez, and Krste Asanović, "SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine", Fourth Workshop on Computer Architecture Research with RISC-V (CARRV 2020) at the 47th International Symposium on Computer Architecture (ISCA-2020), May 2020. PDF

• Gui Andrade, Dayeol Lee, David Kohlbrenner, Krste Asanović, and Dawn Song, "Software-Based Off-Chip Memory Protection for RISC-V Trusted Execution Environments", Fourth Workshop on Computer Architecture Research with RISC-V (CARRV 2020) at the 47th International Symposium on Computer Architecture (ISCA-2020), May 2020. PDF

• Dayeol Lee, David Kohlbrenner, Shweta Shinde, Krste Asanović, and Dawn Song, "Keystone: An Open Framework for Architecting Trusted Execution Environments", Fifteenth European Conference on Computer Systems (EuroSys '20), Heraklion, Greece, April 2020.

• Ckristian Duran, Megan Wachs, Luis Rueda, Albert Huntington, Hector Gomez, Javier Ardila, Andres Amaya, Krste Asanović, Elkim Roa, "An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications", 2020 IEEE Custom Integrated Circuits Conference (CICC-2020), Boston, MA, March 2020.

• Sagar Karandikar, Albert Ou, Alon Amid, Howard Mao, Randy Katz, Borivoje Nikolić, and Krste Asanović, "FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design", 25th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2020), Lausanne, Switzerland, March 2020.

• Ameer Haj-Ali, Qijing Huang, John Xiang, William Moses, Krste Asanović, John Wawrzynek, and Ion Stoica, "AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning", Third Conference on Machine Learning and Systems (MLSys-2020), Austin, TX, March 2020.

• Ameer Haj-Ali, Nesreen K. Ahmed, Ted Willke, Yakun Sophia Shao, Krste Asanović, and Ion Stoica, "NeuroVectorizer: End-to-End Vectorization with Deep Reinforcement Learning", International Symposium on Code Generation and Optimization (CGO-2020), San Diego, February 2020. PDF

2019

• Albert Magyar, David Biancolin, Jack Koenig, Sanjit Seshia, Jonathan Bachrach, Krste Asanović, "Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes", 2019 International Conference On Computer-Aided Design (ICCAD-2019), Westminster, CO, November 2019.

• Qijing Huang, Christopher Yarp, Sagar Karandikar, Nathan Pemberton, Benjamin Brock, Liang Ma, Guohao Dai, Robert Quitt, Krste Asanović, John Wawrzynek, "Centrifuge: Evaluating Full-System HLS-Generated Heterogenous-Accelerator SoCs using FPGA-Acceleration", 2019 International Conference On Computer-Aided Design (ICCAD-2019), Westminster, CO, November 2019.

• Donggyu Kim, Jerry Zhao, Jonathan Bachrach, and Krste Asanović, "Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection", 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-52), Columbus, OH, October 2019.

• Abraham Gonzalez, Ben Korpan, Jerry Zhao, Ed Younis, and Krste Asanović, "Replicating and Mitigating Spectre Attacks on a Open-Source RISC-V Microarchitecture", Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019), at the 46th International Symposium on Computer Architecture (ISCA-2019), Phoenix, AZ, June 2019.

• Sagar Karandikar, David Biancolin, Alon Amid, Nathan Pemberton, Albert Ou, Randy Katz, Borivoje Nikolić, Jonathan Bachrach and Krste Asanović, "Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research", Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019), at the 46th International Symposium on Computer Architecture (ISCA-2019), Phoenix, AZ, June 2019.

• Alon Amid, Albert Ou, Krste Asanović and Borivoje Nikolić, "Nested-Parallelism PageRank on RISC-V Vector Multi-Processors", Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019), at the 46th International Symposium on Computer Architecture (ISCA-2019), Phoenix, AZ, June 2019.

• Elad Alon, Krste Asanović, Jonathan Bachrach, and Borivoje Nikolíć, "Open-Source EDA Tools and IP, A View from the Trenches", Design Automation Conference (DAC-2019), Las Vegas, NV, June 2019. PDF
  Invited paper.

• Qijing Huang, Ameer Haj-Ali, William Moses, John Xiang, Ion Stoica, Krste Asanović, and John Wawrzynek, "AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning", IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM-2019), San Diego, CA, May 2019.

• Ilia Lebedev, Kyle Hogan, Jules Drean, David Kohlbrenner, Dayeol Lee, Krste Asanović, Dawn Song, and Srini Devadas, Sanctorum: A Lightweight Security Monitor for Secure Enclaves, Design, Automation, and Test in Europe (DATE'19), February 2019.

• David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanović, "FASED: FPGA-Accelerated Simulation and Evaluation of DRAM", 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2019), Seaside, California, February 2019.

• Lisa Wu, David Bruns-Smith, Frank A. Nothaft, Qijing Huang, Sagar Karnadikar, Johnny Le, Andrew Lin, Howard Mao, Brendan Sweeney, Krste Asanović, David A. Patterson, Anthony D. Joseph, "FPGA Accelerated INDEL Realignment in the Cloud", 25th International Symposium on High-Performance Computer Architecture (HPCA 2019), Washington, DC, February 2019.

2018

• Borivoje Nikolić, Elad Alon, and Krste Asanović, "Generating the Next Wave of Custom Silicon", IEEE 44th European Solid-State Circuits Conference (ESSCIRC-2018), September 2018.
  Invited paper.

• Donggyu Kim, Chris Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, and Krste Asanović, "DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles", 28th International Conference on Field-Programmable Logic and Applications (FPL-2018), Dublin, Ireland, August 2018.

• Christopher Celio, Pi-Feng Chiu, Krste Asanović, David Patterson, and Borivoje Nikolić, "BROOM: An Open-Source Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28nm CMOS", Hot Chips 30, Cupertino, CA, August 2018.

• Alon Amid, Amir Gholami, Kiseok Kwon, Bichen Wu, Krste Asanović, and Kurt Keutzer, "Co-Design of Neural Nets and Neural Net Accelerators for Embedded Vision Applications", Design Automation Conference (DAC-2018), San Francisco, CA, June 2018. arXiv

• Pi-Feng Chiu, Christopher Celio, Krste Asanović, David Patterson, and Borivoje Nikolić, "An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28nm CMOS", Symposium on VLSI Circuits (VLSI-2018), Honolulu, HI, June 2018.

• Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, "FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud", International Symposium on Computer Architecture (ISCA-2018), Los Angeles, CA, June 2018.
  Selected as one of IEEE Micro's "Top Picks from Computer Architecture Conferences, 2018".

• Martin Maas, Krste Asanović, and John Kubiatowicz, "A Hardware Accelerator for Tracing Garbage Collection", International Symposium on Computer Architecture (ISCA-2018), Los Angeles, CA, June 2018. PDF
  Selected as one of IEEE Micro's "Top Picks from Computer Architecture Conferences, 2018".

• Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, and Krste Asanović, "Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud", Second Workshop on Computer Architecture Research with RISC-V (CARRV 2018), at the 45th International Symposium on Computer Architecture (ISCA-2018), Los Angeles, CA, June 2018.

• Lisa Wu, Frank Nothaft, Brendan Sweeney, David Bruns-Smith, Sagar Karandikar, Johnny Le, Howard Mao, Krste Asanović, David Patterson and Anthony Joseph, "Accelerating Duplicate Marking In The Cloud", Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB), at the 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2018), Vienna, Austria, February, 2018.

2017

• Jonathan Bachrach, Albert Magyar, Palmer Dabbelt, Patrick Li, Richard Lin, Krste Asanović, "Cyclist: Accelerating Hardware Development", 2017 International Conference on Computer-Aided Design (ICCAD-2017), Irvine, CA, November 2017. PDF

• Martin Maas, Krste Asanović, and John Kubiatowicz "Full-System Simulation of Java Workloads With RISC-V and the Jikes Research Virtual Machine", Workshop on Computer Architecture Research using RISC-V (CARRV-2017), at the 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-50), Boston, MA, October 2017. PDF

• Donggyu Kim, Christopher Celio, David Biancolin, Jonathan Bachrach, and Krste Asanović, "Evaluation of RISC-V RTL Designs with FPGA Simulation", Workshop on Computer Architecture Research using RISC-V (CARRV-2017), at the 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-50), Boston, MA, October 2017. PDF

• Christopher Celio, Pi-Feng Chiu, Borivoje Nikolić, David Patterson, and Krste Asanović, "BOOMv2: an open-source out-of-order RISC-V core", Workshop on Computer Architecture Research using RISC-V (CARRV-2017), at the 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-50), Boston, MA, October 2017. PDF

• Jack Koenig, David Biancolin, Jonathan Bachrach, and Krste Asanović, "A Hardware Accelerator for Computing an Exact Dot Product", 24th IEEE Symposium on Computer Arithmetic (ARITH-24), London, UK, July 2017. PDF

• Scott Beamer, Krste Asanović, and David Patterson, "Reducing Pagerank Communication via Propagation Blocking", 31st IEEE International Parallel and Distributed Processing Symposium (IPDPS-2017), Orlando, FL, May 2017.
  Winner, Best Paper - Algorithms Track

• Martin Maas, Krste Asanović, and John Kubiatowicz, "Return of the Runtimes: Rethinking the Language Runtime System for the Cloud 3.0 Era", 16th Workshop on Hot Topics in Operating Systems (HotOS-XVI), Vancouver, Canada, May 2017. PDF

• Chen Sun, Mark Wade, Yunsup Lee, Jason Orcutt, Luca Alloatti, Michael Georgas, Andrew Waterman, Jeffrey Shainline, Rimas Avižienis, Sen Lin, Benjamin Moss, Rajesh Kumar, Fabio Pavanello, Amir Atabaki, Henry Cook, Albert Ou, Jonathan Leu, Yu-Hsin Chen, Krste Asanović, Rajeev Ram, Milos A. Popović, Vladimir Stojanović, "Microprocessor Chip with Photonics I/O", Optical Fiber Communication Conference, Los Angeles, CA, March 2017.

2016

• Brian Zimmer, Pi-Feng Chiu, Borivoje Nikolić, and Krste Asanović, "Reprogrammable Redundancy for Cache Vmin Reduction in a 28nm RISC-V processor", IEEE Asian Solid-State Circuits Conference (A-SSCC 2016), Toyama, Japan, November 2016.

• Ben Keller, Martin Cochet, Brian Zimmer, Yunsup Lee, Milovan Blagojević, Jaehwa Kwak, Alberto Puggelli, Stevo Bailey, Pi-Feng Chiu, Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanović, and Borivoje Nikolić, "Sub-microsecond Adaptive Voltage Scaling in a 28nm FD-SOI Processor SoC", 2016 European Solid-State Circuits Conference (ESSCIRC-2016), Lausanne, Switzerland, September 2016.

• Donggyu Kim, Adam Izraelevitz, Christopher Celio, Hokeun Kim, Brian Zimmer, Yunsup Lee, Jonathan Bachrach, and Krste Asanović, "Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL", International Symposium on Computer Architecture (ISCA-2016), Seoul, Korea, June 2016. PDF
  Honorable Mention in IEEE Micro's "Top Picks from Computer Architecture Conferences, 2016"

• Palmer Dabbelt, Colin Schmidt, Eric Love, Howard Mao, Sagar Karandikar and Krste Asanović, "Vector Processors for Energy-Efficient Embedded Systems", Fourth International Workshop on Manycore Embedded Systems (MES 2016), at the International Symposium on Computer Architecture (ISCA-2016), Seoul, Korea, June 2016. PDF

• Martin Maas, Krste Asanović, and John Kubiatowicz, "Grail Quest: A New Proposal for Hardware-Assisted Garbage Collection", Sixth Workshop on Architectures and Systems for Big Data (ASBD 2016), at the International Symposium on Computer Architecture (ISCA-2016), Seoul, Korea, June 2016. PDF

• Martin Maas, Krste Asanović, Tim Harris, and John Kubiatowicz, "Taurus: A Holistic Language Runtime System for Coordinating Distributed Managed-Language Applications", 21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2016), Atlanta, GA, April 2016.

• Brian Zimmer, Pi-Feng Chiu, Krste Asanović, and Borivoje Nikolić, "Circuit and Architectural Techniques for Minimum-energy Operation of SRAM-based Caches", 1st International Workshop on Emerging Memory Solutions, IEEE/ACM Design, Automation and Test in Europe Conference (DATE-2016), Dresden, Germany, March 2016.

2015

• Scott Beamer, Krste Asanović, and David Patterson, "GAIL: The Graph Algorithm Iron Law", 5th Workshop on Irregular Applications: Architectures and Algorithms (IA3-2015), at the International Conference for High Performance Computing, Networking, Storage and Analysis (Supercomputing'15), Austin, Texas, November 2015. PDF

• Scott Beamer, Krste Asanović, and David Patterson, "Locality Exists in Graph Processing: Workload Characterization on an Ivy Bridge Server", IEEE International Symposium on Workload Characterization (IISWC-2015), Atlanta, October 2015. PDF
  Winner, Best Paper Award, IISWC 2015

• Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ružica Jevtić, Ben Keller, Stevo Bailey, Milovan Blagojević, Pi-Feng Chiu, Henry Cook, Rimas Avižienis, Brian Richards, Elad Alon, Borivoje Nikolić, and Krste Asanović, "Raven: a 28nm RISC-V Vector Processor with Integrated Switched-Capacitor DC-DC Converters and Adaptive Clocking", Hot Chips 27, Cupertino, CA, August 2015.

• Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ružica Jevtić, Ben Keller, Stevo Bailey, Milovan Blagojević, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avižienis, Andrew Waterman, Brian Richards, Philippe Flatresse, Elad Alon, Krste Asanović, and Borivoje Nikolić, "A RISC-V Vector Processor with Tightly-Integrated Switched-Capacitor DC-DC Converters in 28nm FDSOI", 2015 Symposia on VLSI Technology and Circuits (VLSI-2015), Kyoto, Japan, June 2015.

• Martin Maas, Tim Harris, Krste Asanović, and John Kubiatowicz, "Trash Day: Coordinating Garbage Collection in Distributed Systems", 15th Workshop on Hot Topics in Operating Systems (HotOS-XV), Kartause Ittengen, Switzerland, May 2015. PDF

• Zhangxi Tan, Zhanghao Qian, Xi Chen, Krste Asanović, and David A. Patterson, "DIABLO: A Warehouse-Scale Computer Network Simulator using FPGAs", 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2015), Istanbul, Turkey, March 2015. ACM DL

2014

• Yunsup Lee, Vinod Grover, Ronny Krashinsky, Mark Stephenson, Stephen W. Keckler, and Krste Asanović, "Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures", 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-47), Cambridge, UK, December 2014. PDF

• Yunsup Lee, Andrew Waterman, Rimas Avižienis, Henry Cook, Chen Sun, Vladimir Stojanović, and Krste Asanović, "A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V Processor with Vector Accelerators", 2014 European Solid-State Circuits Conference (ESSCIRC-2014), Venice, Italy, September, 2014. PDF

• Brian Zimmer, Olivier Thomas, Seng Oon Toh, Taylor Vincent, Krste Asanović, and Borivoje Nikolić, "Joint Impact of Random Variations and RTN on Dynamic Writability in 28nm Bulk and FDSOI SRAM", 2014 European Solid-State Device Research Conference (ESSDERC-2014), Venice, Italy, September 2014. PDF

• Jeff Bilmes, Krste Asanović, Chee-Whye Chin, and Jim Demmel, "Author Retrospective for 'Optimizing matrix multiply using PHiPAC: a portable, high-performance, ANSI C coding methodology' ", ACM International Conference on Supercomputing 25th Year Anniversary Volume (ICS'14), Munich, Germany, June 2014. ACM DL
  One of 35 papers selected out of around 1800 papers published from 1987-2011

• Albert Ou, Quan Nguyen, Yunsup Lee, Krste Asanović, "A Case for MVPs: Mixed-Precision Vector Processors", 2nd International Workshop on Parallelism in Mobile Platforms (PRISM-2), at the International Symposium on Computer Architecture (ISCA-2014), Minneapolis, MN, June 2014.

• Martin Maas, Krste Asanović, Tim Harris, John Kubiatowicz, "The Case for the Holistic Language Runtime System", First International Workshop on Rack-Scale Computing (WRSC 2014), at the European Conference on Computer Systems (EuroSys 2014), Amsterdam, The Netherlands, April 2014. PDF

2013

• Martin Maas, Eric Love, Emil Stefanov, Mohit Tiwari, Elaine Shi, Krste Asanović, John Kubiatowicz, Dawn Song, "A High-Performance Oblivious RAM Controller on the Convey HC-2ex Heterogeneous Computing Platform", 3rd Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2013), at the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46), Davis, California, December 2013. PDF

• Martin Maas, Eric Love, Emil Stefanov, Mohit Tiwari, Elaine Shi, Krste Asanović, John Kubiatowicz, Dawn Song, "PHANTOM: Practical Oblivious Computation in a Secure Processor", ACM Conference on Computer and Communications Security (CCS-2013), Berlin, Germany, November 2013. ACM DL
  Top 10 Finalist, Best Applied Security Paper Contest, CSAW 2013

• Huy Vo, Yunsup Lee, Andrew Waterman, Krste Asanović, "A Case for OS-Friendly Hardware Accelerators", 7th Annual Workshop on the Interaction between Operating System and Computer Architecture (WIVOSCA-2013), at the International Symposium on Computer Architecture (ISCA-2013), Tel Aviv, Israel, June 2013. PDF

• Henry Cook, Miquel Moretó, Sarah Bird, Khanh Dao, David Patterson, Krste Asanović, "A Hardware Evaluation of Cache Partitioning to Improve Utilization and Energy-Efficiency while Preserving Responsiveness", International Symposium on Computer Architecture (ISCA-2013), Tel Aviv, Israel, June 2013. PDF

• Juan A. Colmenares, Gage Eads, Steven Hofmeyr, Sarah Bird, Miquel Moretó, David Chou, Brian Gluzman, Eric Roman, Davide B. Bartolini, Nitesh Mor, Krste Asanović, John D. Kubiatowicz, "Tessellation: Refactoring the OS around Explicit Resource Containers with Continuous Adaptation", Design Automation Conference (DAC-2013), Austin, TX, June 2013. PDF

• Scott Beamer, Aydın Buluç, Krste Asanović, David Patterson, "Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search", Workshop on Multithreaded Architectures and Applications (MTAAP-2013), at the International Parallel & Distributed Processing Symposium (IPDPS-2013), Boston, May 2013. PDF

• Yunsup Lee, Ronny Krashinsky, Vinod Grover, Stephen W. Keckler, Krste Asanović, "Convergence and Scalarization for Data-Parallel Architectures", International Symposium on Code Generation and Optimization (CGO 2013), Shenzhen, China, February 2013. PDF

2012

• Scott Beamer, Krste Asanović, David Patterson, "Direction-Optimizing Breadth-First Search", International Conference for High Performance Computing, Networking, Storage, and Analysis (SC12), Salt Lake City, UT, November 2012.
  Best Student Paper Finalist PDF

• Mohit Tiwari, Prashanth Mohan, Andrew Osheroff, Hilfi Alkaff, Elaine Shi, Eric Love, Dawn Song, Krste Asanović, "Context-centric Security", 7th Usenix Workshop on Hot Topics in Security (HotSec'12), Bellevue, WA, August 2012. PDF

• Martin Maas, Philip Reames, Jeffrey Morlan, Krste Asanović, Anthony D. Joseph, John Kubiatowicz, "GPUs: An Opportunity for Offloading Garbage Collection", International Symposium on Memory Management (ISMM-2012), Beijing, China, June 2012. PDF

• Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avižienis, John Wawrzynek, Krste Asanović, "Chisel: Constructing Hardware in a Scala Embedded Language", Design Automation Conference (DAC-2012), San Francisco, CA, June 2012. PDF

2011

• Juan Colmenares, Ian Saxton, Eric Battenberg, Rimas Avizienis, Nils Peters, Krste Asanović, John Kubiatowicz, and David Wessel, "Real-time musical applications on an experimental operating system for multi-core processors", 2011 International Computer Music Conference (ICMC-2011), Huddersfield, England, July 2011. PDF

• Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, and Krste Asanović, "Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators", International Symposium on Computer Architecture (ISCA-2011), San Jose, CA, June 2011. PDF

• Zhangxi Tan, Krste Asanović, and David A. Patterson, "Datacenter-Scale Network Research on FPGAs", The Exascale Evaluation and Research Techniques Workshop (EXERT 2011), at the 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2011), Newport Beach, CA, March 2011. PDF

2010

• Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanović, David A. Patterson, "A Case for FAME: FPGA Architecture Model Execution", International Symposium on Computer Architecture (ISCA-2010), Saint-Malo, France, June 2010. PDF

• Scott Beamer, Chen Sun, Yong-jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanović, Krste Asanović, "Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics", International Symposium on Computer Architecture (ISCA-2010), Saint-Malo, France, June 2010. PDF

• Juan A. Colmenares, Sarah Bird, Henry Cook, Paul Pearce, David Zhu, John Shalf, Krste Asanović, and John Kubiatowicz, "Resource Management in the Tessellation Manycore OS", 2nd USENIX Workshop on Hot Topics in Parallelism (HotPar '10), Berkeley, CA, June 2010. PDF

• Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanović, "RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors", Design Automation Conference (DAC-2010), Anaheim, CA, June 2010. PDF

• Heidi Pan, Benjamin Hindman, and Krste Asanović, "Composing Parallel Software Efficiently with Lithe", Programming Language Design and Implementation (PLDI-2010), Toronto, Canada, June 2010. PDF

• Vladimir Stojanović, Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Chen Sun, Krste Asanović, "A Design-Space Exploration for CMOS Photonic Processor Networks", Optical Fiber Communication Conference and Exposition and The National Fiber Optic Engineers Conference (OFC/NFOEC), San Diego, CA, March 2010.
  Invited paper. PDF

• Zhangxi Tan, Krste Asanović, and David A. Patterson, "An FPGA-Based Simulator for Datacenter Networks", The Exascale Evaluation and Research Techniques Workshop (EXERT 2010), at the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010), Pittsburgh, PA, March 2010. PDF

2009

• Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanović, and Vladimir Stojanović, "Limits and Opportunities for Designing Manycore Processor-to-Memory Networks using Monolithic Silicon Photonics", Workshop on Photonic Interconnects & Computer Architecture (PICA), at the 42nd ACM/IEEE International Symposium on Microarchitecture (MICRO-42), New York, NY, December 2009. PDF

• Bryan Catanzaro, Shoaib Kamil, Yunsup Lee, Krste Asanović, James Demmel, Kurt Keutzer, John Shalf, Kathy Yelick, Armando Fox, "SEJITS: Getting Productivity AND Performance With Selective Embedded JIT Specialization", First Workshop on Programming Models for Emerging Architectures (PMEA), at the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT'09), Raleigh, NC, September 2009. PDF
  Also available as UCB Technical Report UCB/EECS-2010-23.

• Scott Beamer, Krste Asanović, Christopher Batten, Ajay Joshi, and Vladimir Stojanović, "Designing Multi-socket Systems Using Silicon Photonics", 23rd International Conference on Supercomputing (ICS-09), Yorktown Heights, NY, June 2009. (ACM DL) PDF

• Vladimir Stojanović, Ajay Joshi, Christopher Batten, Yong-Jin Kwon, and Krste Asanović, "Manycore processor networks with monolithic integrated CMOS photonics", 29th Conference on Lasers and Electro-Optics (CLEO'09), Baltimore, MD, June 2009. PDF
  Invited paper.

• Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanović and Vladimir Stojanović, "Silicon-Photonic Clos Networks for Global On-Chip Communication", 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS), San Diego, CA, May 2009. PDF

• Christopher Grant Jones, Rose Liu, Leo Meyerovich, Krste Asanović, and Rastislav Bodik, "Parallelizing the Web Browser", First USENIX Workshop on Hot Topics in Parallelism (HotPar'09), Berkeley, CA, March 2009. PDF

• Rose Liu, Kevin Klues, Sarah Bird, Steven Hofmeyr, Krste Asanović, and John Kubiatowicz, "Tessellation: Space-Time Partitioning in a Manycore Client OS", First USENIX Workshop on Hot Topics in Parallelism (HotPar'09), Berkeley, CA, March 2009. PDF

• Heidi Pan, Benjamin Hindman, and Krste Asanović, "Lithe: Enabling Efficient Composition of Parallel Libraries", First USENIX Workshop on Hot Topics in Parallelism (HotPar'09), Berkeley, CA, March 2009. PDF

2008

• Christopher Batten, Hidetaka Aoki, and Krste Asanović, "The Case for Malleable Stream Architectures", Workshop on Streaming Systems at 41st International Symposium on Microarchitecture (MICRO-41), Lake Como, Italy, November 2008. PDF

• Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Miloš Popović, Hanqing Li, Henry Smith, Judy Hoyt, Franz Kärtner, Rajeev Ram, Vladimir Stojanović, and Krste Asanović, "Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics", 16th Annual IEEE Symposium on High-Performance Interconnects (Hot Interconnects 2008), Stanford, CA, August 2008. PDF

• Daniel Burke, John Wawrzynek, Krste Asanović, Alex Krasnov, Andrew Schultz, Greg Gibeling, Pierre-Yves Droz, "RAMP Blue: Implementation of a Multicore 1008 Processor FPGA System", Reconfigurable Systems Summer Institute, Urbana, IL, July 2008. PDF

• Zhangxi Tan, Krste Asanović, and David A. Patterson, "An FPGA Host-Multithreaded Functional Model for SPARC v8", 3rd Workshop on Architectural Research Prototyping (WARP-2008), at 35th International Symposium on Computer Architecture (ISCA-35), Beijing, China, June 2008. PDF

• Jae W. Lee, Man Cheuk Ng, and Krste Asanović, "Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks", 35th International Symposium on Computer Architecture (ISCA-35), Beijing, China, June 2008. PDF

• Mark Hampton and Krste Asanović, "Compiling for Vector-Thread Architectures", International Symposium on Code Generation and Optimization (CGO-2008), Boston, MA, April 2008. PDF

2007

• Krste Asanović, "Transactors for Parallel Hardware and Software Co-Design", IEEE International High Level Design Validation and Test Workshop 2007 (HLDVT-2007), Irvine, CA, November 2007. PDF
  Invited paper.

• Jae W. Lee, Myron King, and Krste Asanović, "Continual Hashing for Efficient Fine-Grain State Inconsistency Checking", IEEE International Conference on Computer Design (ICCD-2007), Lake Tahoe, CA, October 2007. PDF
  

• Ronny Krashinsky, Christopher Batten, and Krste Asanović, "The Scale Vector-Thread Processor",
  Winner, DAC/ISSCC Student Design Contest, February/June 2007.

2006

• Stephen Crago, Janice Onanian McMahon, Chris Archer, Krste Asanović, Richard Chaung, Keith Goolsbey, Mary Hall, Christos Kozyrakis, Kunle Olukotun, Una-May O'Reilly, Rick Pancoast, Viktor Prasanna, Rodric Rabbah, Steve Ward, Donald Yeung, "CEARCH: Cognition Enabled Architecture", Proceedings of the 10th Workshop on High Performance Embedded Computing (HPEC), Lexington, MA, September 2006. PDF

• David A. Patterson, Arvind, Krste Asanović, Derek Chiou, James C. Hoe, Christoforos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan Rabaey, and John Wawrzynek, "RAMP: Research Accelerator for Multiple Processors", Hot Chips 18, Stanford, CA, August 2006. PDF

• Vern Paxson, Krste Asanović, Sarang Dharmapurikar, John W. Lockwood, Ruoming Pang, Robin Sommer, Nicholas C. Weaver, "Rethinking Hardware Support for Network Analysis and Intrusion Prevention", 1st Workshop on Hot Topics in Security (HotSec'06), Vancouver, Canada, July 2006. PDF

• Mark Hampton and Krste Asanović, "Implementing Virtual Memory in a Vector Processor with Software Restart Markers", 20th ACM International Conference on Supercomputing (ICS06), Cairns, Australia, June 2006. PDF

• Jae W. Lee and Krste Asanović, "METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors", 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2006), San Jose, CA, April 2006. PDF

• Rose F. Liu and Krste Asanović, "Accelerating Architectural Exploration Using Canonical Instruction Segments", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2006), Austin, TX, March 2006. PDF

• Kenneth C. Barr and Krste Asanović, "Branch Trace Compression for Snapshot-Based Simulation", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2006), Austin, TX, March 2006. PDF

• Greg Gibeling, Andrew Schultz, and Krste Asanović, "The RAMP Architecture & Description Language", 2nd Workshop on Architecture Research using FPGA Platforms (WARFP-2006), at 12th International Symposium on High Performance Computer Architecture (HPCA-12), Austin, Texas, February 2006. PDF

2005

• Emmett Witchel, Junghwan Rhee, Krste Asanović, "Mondrix: Memory Isolation for Linux using Mondriaan Memory Protection", 20th ACM Symposium on Operating Systems Principles (SOSP-20) Brighton, UK, October 2005. PDF

• Heidi Pan, Krste Asanović, Robert Cohn, and Chi-Keung Luk, "Controlling Program Execution through Binary Instrumentation", Workshop on Binary Instrumentation and Applications (WBIA-2005), at 14th International Conference on Parallel Architectures and Compilation Techniques (PACT-14), St. Louis, MO, September 2005. PDF

• Seongmoo Heo and Krste Asanović, "Replacing Global Wires with an On-Chip Network: A Power Analysis", International Symposium on Low Power Electronics and Design (ISLPED'05), San Diego, CA, August 2005. PDF

• Michael Zhang and Krste Asanović, "Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled CMPs", 32nd International Symposium on Computer Architecture (ISCA-32), Madison, WI, June 2005. PDF

• Kenneth C. Barr, Heidi Pan, Michael Zhang, and Krste Asanović, "Accelerating Multiprocessor Simulation with a Memory Timestamp Record", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005), Austin, TX, March 2005. PDF

• C. Scott Ananian, Krste Asanović, Bradley C. Kuszmaul, Charles E. Leiserson, and Sean Lie, "Unbounded Transactional Memory", 11th International Symposium on High Performance Computer Architecture (HPCA-11), San Francisco, CA, February 2005. PDF
  Selected as one of IEEE Micro's "Top Picks from Computer Architecture Conferences, 2005".

• Jared Casper, Ronny Krashinsky, Christopher Batten, and Krste Asanović, "A Parameterizable FPGA Prototype of a Vector-Thread Processor", 1st Workshop on Architecture Research using FPGA Platforms (WARFP-2005), at 11th International Symposium on High Performance Computer Architecture (HPCA-11), San Francisco, CA, February 2005. PDF

2004

• Christopher Batten, Ronny Krashinsky, Steven Gerding, and Krste Asanović, "Cache Refill/Access Decoupling for Vector Machines", 37th International Symposium on Microarchitecture (MICRO-37), Portland, OR, December 2004. PDF

• Seongmoo Heo and Krste Asanović, "Power-Optimal Pipelining in Deep Submicron Technology", International Symposium on Low Power Electronics and Design (ISLPED'04), Newport Beach, CA, August 2004. PDF

• Ronny Krashinsky, Christopher Batten, Mark Hampton, Steven Gerding, Brian Pharris, Jared Casper, and Krste Asanović, "The Vector-Thread Architecture", 31st International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004. PDF
  Selected as one of IEEE Micro's "Top Picks from Computer Architecture Conferences, 2004".

2003

• Seongmoo Heo, Kenneth C. Barr, and Krste Asanović, "Reducing Power Density through Activity Migration", International Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, August 2003. PDF

• Jessica Tseng and Krste Asanović, "Banked Multiported Register Files for High-Frequency Superscalar Microprocessors", 30th International Symposium on Computer Architecture (ISCA-30), San Diego, CA, June 2003. PDF

• Emmett Witchel and Krste Asanović, "Hardware Works, Software Doesn't: Enforcing Modularity with Mondriaan Memory Protection", Ninth Workshop on Hot Topics in Operating Systems (HotOS-IX), Lihue, HI, May 2003. PDF

• Kenneth C. Barr and Krste Asanović, "Energy Aware Lossless Data Compression", First International Conference on Mobile Systems, Applications, and Services (MobiSys-2003) , San Francisco, CA, May 2003. PDF
  Winner, Best Paper Award, MobiSys 2003.

2002

• Emmett Witchel, Josh Cates, and Krste Asanović, "Mondrian Memory Protection", Tenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X) , San Jose, CA, October 2002. PDF

• Michael Zhang and Krste Asanović, "Miss Tags for Fine-Grain CAM-Tag Cache Resizing", International Symposium on Low Power Electronics and Design (ISLPED'02), Monterey, CA, August 2002. PDF

• Seongmoo Heo and Krste Asanović, "Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction", 2002 Symposium on VLSI Circuits (VLSI-2002), Honolulu, HI, June 2002. PDF

• Seongmoo Heo, Kenneth C. Barr, Mark Hampton, and Krste Asanović, "Dynamic Fine-Grain Leakage Reduction using Leakage-Biased Bitlines", 29th International Symposium on Computer Architecture (ISCA-29), Anchorage, AK, May 2002. PDF

2001

• Emmett Witchel, Sam Larsen, C. Scott Ananian, and Krste Asanović, "Direct Addressed Caches for Reduced Power Consumption", 34th International Symposium on Microarchitecture (MICRO-34), Austin, TX, December 2001. PDF

• Heidi Pan and Krste Asanović, "Heads and Tails: A Variable-Length Instruction Format Supporting Parallel Fetch and Decode", International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), Atlanta, GA, November 2001. PDF

• Michael Sung, Ronny Krashinsky, and Krste Asanović, "Multithreading Decoupled Architectures for Complexity-Effective General Purpose Computing", Workshop on Memory Access Decoupled Architectures (MEDEA'01), at International Conference on Parallel Architectures and Compilation Techniques (PACT'01), Barcelona, Spain, September 2001. PDF

• Emmett Witchel and Krste Asanović, "The Span Cache: Software Controlled Tag Checks and Cache Line Size", Workshop on Complexity-Effective Design, at 28th International Symposium on Computer Architecture (ISCA-28), Goteborg, Sweden, June 2001. PDF

• Albert Ma, Michael Zhang, and Krste Asanović, "Way Memoization to Reduce Fetch Energy in Instruction Caches", Workshop on Complexity-Effective Design, at 28th International Symposium on Computer Architecture (ISCA-28), Goteborg, Sweden, June 2001. PDF

• Seongmoo Heo and Krste Asanović, "Load-Sensitive Flip-Flop Characterization", IEEE Workshop on VLSI, Orlando, FL, April 2001. PDF

• Seongmoo Heo, Ronny Krashinsky, and Krste Asanović, "Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy", 19th Conference on Advanced Research in VLSI (ARVLSI 2001), Salt Lake City, UT, March 2001. PDF

2000

• Michael Zhang and Krste Asanović, "Highly-Associative Caches for Low-Power Processors", Kool Chips Workshop, at 33rd International Symposium on Microarchitecture (MICRO-33), Monterey, CA, December 2000. PDF

• Luis Villa, Michael Zhang, and Krste Asanović, "Dynamic Zero Compression for Cache Energy Reduction", 33rd International Symposium on Microarchitecture (MICRO-33), Monterey, CA, December 2000. PDF

• Jessica Tseng and Krste Asanović, "Energy-Efficient Register Access", SBCCI2000, XIII Symposium on Integrated Circuits and System Design, Manaus, Amazonas, Brazil, September 2000. PDF

• Ronny Krashinsky, Seongmoo Heo, Michael Zhang, and Krste Asanović, "SyCHOSys: Compiled Energy-Performance Cycle Simulation", Workshop on Complexity-Effective Design, at 27th International Symposium on Computer Architecture (ISCA-27), June 2000. PDF

• Krste Asanović, "Energy-Exposed Instruction Set Architectures", Work In Progress Session, Sixth International Symposium on High Performance Computer Architecture (HPCA-6), Toulouse, France, January 2000. Published in IEEE TCCA newsletter, June 2000. PDF

Pre-1998

• Philipp Faerber and Krste Asanović, "Parallel neural network training on Multi-Spert", IEEE 3rd International Conference on Algorithms and Architectures for Parallel Processing, Special session on Parallel Algorithms and Architectures for Neural Processing, Melbourne, Australia, December 1997. Postscript, PDF.

• David A. Patterson, Krste Asanović, Aaron Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos Kozyrakis, David Martin, Stylianos Perissakis, Randi Thomas, Noah Treuhaft, and Katherine Yelick. "Intelligent RAM (IRAM): the industrial setting, applications, and architecture", International Conference on Computer Design (ICCD'97), Austin, Texas, 10-12 October 1997. PDF

• Jeff Bilmes, Krste Asanović, Chee-Whye Chin, and Jim Demmel, "Optimizing matrix multiply using PHiPAC: a portable, high-performance, ANSI C coding methodology", 11th ACM International Conference on Supercomputing (ICS'97), July 1997. PDF

• Krste Asanović, "A fast Kohonen net implementation for Spert-II", IWANN''97, Lanzarote, Canary Islands, Spain, June 1997. PDF

• Jeff Bilmes, Krste Asanović, Chee-Whye Chin, and Jim Demmel, "Using PHiPAC to speed error back-propagation learning", International Conference on Acoustics, Speech, and Signal Processing (ICASSP'97), Munich, Germany, April 1997, Volume 5, pp4153-4157. PDF

• Krste Asanović, Brian Kingsbury, Bertrand Irissou, James Beck, and John Wawrzynek "T0: A single-chip vector microprocessor with reconfigurable pipelines", In Proceedings 22nd European Solid-State Circuits Conference (ESSCIRC'96), Editor: H. Grunbacher, Editions Frontieres, September, 1996, pp344-347. Postscript, PDF

• Krste Asanović, James Beck, Bertrand Irissou, Brian Kingsbury, Nelson Morgan, and John Wawrzynek, "The T0 vector microprocessor", Proceedings HOT Chips VII, Stanford, CA, August 1995. PDF

• Krste Asanović, James Beck, Jerry Feldman, Nelson Morgan, and John Wawrzynek, "A supercomputer for neural computation", Proceedings of the International Conference on Neural Networks, volume 1, pages 5-9, June 1994. PDF

• Krste Asanović, James Beck, Jerry Feldman, Nelson Morgan, and John Wawrzynek, "Development of a Connectionist Network Supercomputer", Proceedings of the Third International Conference on Microelectronics for Neural Networks, pp 253-262, April 1993. A version is available as an ICSI Technical Report TR-93-021.

• Denis B. Howe and Krste Asanović, "SPACE: Symbolic Processing in Associative Computing Elements", VLSI for Neural Networks and Artificial Intelligence, Editors: Jose G. Delgado-Frias and William R. Moore, Plenum Press, 1994, pp 243-252. From Proceedings 3rd International Workshop on VLSI for Artificial Intelligence and Neural Networks, September 1992. HTML, Postscript, PDF

• Krste Asanović, Klaus Erik Schauser, David A. Patterson, and Edward H. Frank, "Evaluation of a stall cache: An efficient restricted on-chip instruction cache", Proceedings 25th Hawaii International Conference on System Sciences pp 405-415, January 1992. PDF
  An expanded version of this paper is available as UCB Technical Report UCB/CSD 91/641.

• Krste Asanović, James Beck, Brian Kingsbury, Phil Kohn, Nelson Morgan, and John Wawrzynek, "SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations", Application Specific Array Processors Conference (ASAP'92), Berkeley, USA, August 1992, pp178-190. A version of this paper is available as ICSI Technical Report TR-91-072.

• Krste Asanović and Nelson Morgan, "Experimental Determination of Precision Requirements for Back-Propagation Training of Artificial Neural Networks", Proceedings 2nd International Conference on Microelectronics for Neural Networks, October 1991, Munich. A version of this paper is available as ICSI Technical Report TR-91-036.

• Krste Asanović, Brian Kingsbury, Nelson Morgan, and John Wawrzynek, "HiPNeT-1: A Highly Pipelined Architecture for Neural Network Training", Proceedings IFIP Workshop on Silicon Architectures for Neural Nets, pp 217-232, November 1990, St Paul de Vence, France. A version of this paper is available as ICSI Technical Report TR-91-035.

• Krste Asanović and James R. Chapman, "Spoken Natural Language Understanding as a Parallel Application", Proceedings CONPAR88, volume B, BCS Parallel Processing Specialist Group, September 1988. Paper (text only) PDF.

Book Chapters

• Ben Keller, Borivoje Nikolić, Brian Zimmer, Martin Cochet, Yunsup Lee, Jaehwa Kwak, Alberto Puggelli, Milovan Blagojević, Ružica Jevtić, Pi-Feng Chiu, Stevo Bailey, Palmer Dabbelt, Colin Schmidt, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avižienis, Andrew Waterman, James Dunn, Brian Richards, Philippe Flatresse, Andrei Vladimirescu, Andreia Cathelin, Elad Alon, and Krste Asanović, "System Integration of RISC-V Processors with FD-SOI", Chapter in The Fourth Terminal: Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems, Sylvain Clerc, Thierry Di Gilio, and Andreia Cathelin (Editors), Springer International Publishing, ISBN 978-3-030-39495-0, April 2020.

• Christopher Batten, Ajay Joshi, Vladimir Stojanović, and Krste Asanović, "Designing Chip-Level Nanophotonic Interconnection Networks", Chapter in Integrated Optical Interconnect Architectures and Applications in Embedded Systems, Gabriela Nicolescu and Ian O'Connor (Editors), Springer, ISBN 978-1-4419-6192-1, 2013. [Extended version of JETCAS paper.] link

• Krste Asanović, "Vector Processing", Chapter in The Computer Engineering Handbook, Second Edition: Digital Systems and Applications, editor Vojin G. Oklobdžija, CRC Press, Taylor and Francis Group, ISBN 9780849386190, November 2007.

• Krste Asanović, John Hennessy, David A. Patterson, "Vector Processors", Appendix F in Computer Architecture: A Quantitative Approach, Fourth Edition, Morgan Kaufman, ISBN 0-12-370490-1, September 2006.

• Krste Asanović, "Programmable Neurocomputing", in The Handbook of Brain Theory and Neural Networks: Second Edition, M. A. Arbib (Ed.), MIT Press, ISBN 0-262-01197-2, November 2002. PDF

• Krste Asanović, John Hennessy, David A. Patterson, "Vector Processors", Appendix G in Computer Architecture: A Quantitative Approach, Third Edition, Morgan Kaufman, ISBN 1-55860-596-7, May 2002. PDF

• Krste Asanović, Mark Hampton, Ronny Krashinsky, Emmett Witchel, "Energy-Exposed Instruction Sets", in Power Aware Computing, Robert Graybill and Rami Melhem (Eds.), Kluwer Academic/Plenum Publishers, ISBN 0-306-46786-0, May 2002. PDF

• Krste Asanović, "Vector Computing", in The Computer Engineering Handbook, Edited by Vojin G. Oklobdžija, CRC Press, ISBN 0849308852, December 2001.

• Krste Asanović, James Beck, David Johnson, John Wawrzynek, Brian E. D. Kingsbury, and Nelson Morgan, "Training Neural Networks with Spert-II". Chapter 11 in Parallel Architectures for Artificial Neural Networks: Paradigms and Implementations, N. Sundararajan and P. Saratchandran (Eds.), IEEE Computer Society Press, ISBN 0-8186-8399-6, November 1998, pp 345-364. PDF

Technical Reports and Other Publications

• Krste Asanović, "SiFive Is Bringing Open Source to the Chip Level", Make Magazine, May 2017.

• Andrew Waterman, Yunsup Lee, Rimas Avižienis, David A. Patterson, and Krste Asanović, "The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.9.1", Technical Report UCB/EECS-2016-161, EECS Department, University of California, Berkeley, November 2016. PDF

• Christopher Celio, Palmer Dabbelt, David Patterson, Krste Asanović, "The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V", Technical Report UCB/EECS-2016-130 EECS Department, University of California, Berkeley, July 2016. PDF

• Andrew Waterman, Yunsup Lee, Rimas Avižienis, David A. Patterson, and Krste Asanović, "The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.9", Technical Report UCB/EECS-2016-129, EECS Department, University of California, Berkeley, July 2016. PDF

• Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanović, "The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.1", Technical Report UCB/EECS-2016-118, EECS Department, University of California, Berkeley, May 2016. PDF

• Krste Asanović, Rimas Avižienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Palmer Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Benjamin Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo, and Andrew Waterman, "The Rocket Chip Generator", Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, April 2016. PDF

• Yunsup Lee, Colin Schmidt, Sagar Karandikar, Daniel Dabbelt, Albert Ou, Krste Asanović, "Hwacha Preliminary Evaluation Results, Version 3.8.1", Technical Report UCB/EECS-2015-264, EECS Department, University of California, Berkeley, December 2015. PDF

• Yunsup Lee, Albert Ou, Colin Schmidt, Sagar Karandikar, Howard Mao, Krste Asanović, "The Hwacha Microarchitecture Manual, Version 3.8.1", Technical Report UCB/EECS-2015-263, EECS Department, University of California, Berkeley, December 2015. PDF

• Yunsup Lee, Colin Schmidt, Albert Ou, Andrew Waterman, Krste Asanović, "The Hwacha Vector-Fetch Architecture Manual, Version 3.8.1", Technical Report UCB/EECS-2015-262, EECS Department, University of California, Berkeley, December 2015. PDF

• Andrew Waterman, Yunsup Lee, David A. Patterson, and Krste Asanović, "The RISC-V Compressed Instruction Set Manual, Version 1.7", Technical Report UCB/EECS-2015-157, EECS Department, University of California, Berkeley, May 2015. PDF

• Andrew Waterman, Yunsup Lee, Rimas Avižienis, David Patterson, and Krste Asanović, "The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.7", Technical Report UCB/EECS-2015-49, EECS Department, University of California, Berkeley, May 2015. PDF

• Krste Asanović and David Patterson, "Instruction Sets Should Be Free: The Case for RISC-V", Technical Report UCB/EECS-2014-146, EECS Department, University of California, Berkeley, August 2014. PDF
  Translation into Russian.

• Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanović, "The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.0", Technical Report UCB/EECS-2014-54, EECS Department, University of California, Berkeley, May 2014. PDF

• Scott Beamer, Krste Asanović, and David A. Patterson, "Searching for a Parent Instead of Fighting Over Children: A Fast Breadth-First Search Implementation for Graph500", Technical Report UCB/EECS-2011-117, EECS Department, University of California, Berkeley, November 2011. PDF

• Andrew Waterman, Yunsup Lee, David A. Patterson, and Krste Asanović, "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA", Technical Report UCB/EECS-2011-62, EECS Department, University of California, Berkeley, May 2011. PDF

• Krste Asanović, Ras Bodik, James Demmel, Tony Keaveny, Kurt Keutzer, John D. Kubiatowicz, Edward A. Lee, Nelson Morgan, George Necula, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel and Katherine A. Yelick, "The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View", Technical Report UCB/EECS-2008-23, EECS Department, University of California, Berkeley, March 2008. PDF

• Christopher Batten, Ronny Krashinsky, and Krste Asanović, "Scale Control Processor Test-Chip", Technical Report MIT-CSAIL-TR-2007-003, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, January 2007. PDF

• Krste Asanović, Ras Bodik, Bryan Christopher Catanzaro, Joseph James Gebis, Parry Husbands, Kurt Keutzer, David A. Patterson, William Lester Plishker, John Shalf, Samuel Webb Williams and Katherine A. Yelick, "The Landscape of Parallel Computing Research: A View from Berkeley", Technical Report UCB/EECS-2006-183, EECS Department, University of California, Berkeley, December 2006. PDF

• Jessica Tseng and Krste Asanović, "RingScalar: A Complexity-Effective Out-of-Order Superscalar Microarchitecture", Technical Report MIT-CSAIL-TR-2006-066, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, September 2006. PDF

• Michael Zhang and Krste Asanović, "Victim Migration: Dynamically Adapting Between Private and Shared CMP Caches", Technical Report, MIT-CSAIL-TR-2005-064, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, October 2005. PDF

• Arvind, Krste Asanović, Derek Chiou, James C. Hoe, Christoforos Kozyrakis, Shih-Lien Lu, Mark Oskin, David A. Patterson, Jan Rabaey, and John Wawrzynek, "RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform", Technical Report UCB/CSD-05-1412, CS Division, University of California, Berkeley, September 2005. PDF

• Seongmoo Heo and Krste Asanović, "Dynamically Resizable Static CMOS Logic for Fine-Grain Leakage Reduction", Technical Report MIT-LCS-TR-957, Laboratory for Computer Science, Massachusetts Institute of Technology, July 2004. PDF

• Rodric M. Rabbah, Ian Bratt, Krste Asanović, and Anant Agarwal, "Versatility and VersaBench: A New Metric and a Benchmark Suite for Flexible Architectures", Technical Memo MIT-LCS-TM-646, Laboratory for Computer Science, Massachusetts Institute of Technology, June 2004. PDF

• Albert Ma and Krste Asanović, "A Double-Pulsed Set-Conditional-Reset Flip-Flop", Technical Report MIT-LCS-TR-844, Laboratory for Computer Science, Massachusetts Institute of Technology, May 2002. PDF

• Jeff Bilmes, Krste Asanović, Chee-Whye Chin, and Jim Demmel, "The PHiPAC v1.0 Matrix-Multiply Distribution". Technical Report TR-98-035, International Computer Science Institute, Berkeley, October 1998. Also listed as UCB CS technical report UCB/CSD-98-1020. PDF

• Krste Asanović and James Beck, "T0 Engineering Data", Technical Report TR-96-057, International Computer Science Institute, Berkeley, December 1996. Also listed as UCB CS technical report UCB/CSD-97-931. PDF

• Krste Asanović and David Johnson, "Torrent Architecture Manual", Technical Report TR-96-056, International Computer Science Institute, Berkeley, December 1996. Also listed as UCB CS technical report UCB/CSD-97-930. PDF

• Jeff Bilmes, Krste Asanović, Jim Demmel, Dominic Lam, and Chee-Whye Chin "Optimizing Matrix Multiply using PHiPAC: a Portable, High-Performance, ANSI C Coding Methodology", LAPACK Working Note 111, Technical Report UT-CS-96-326, University of Tennessee, Knoxville, August 1996. PDF

PhD Theses Supervised

• Dayeol Lee, "Building Trusted Execution Environments", Ph.D. Thesis, University of California, Berkeley, May 2022.
• Keertana Settaluri, "Machine Learning for Acceleration of ASIC Design", Ph.D. Thesis, University of California, Berkeley, August 2021.
• Alon Amid, "Generator-Based Design of Custom Systems-on-Chips for Numerical Data Analysis", Ph.D. Thesis, University of California, Berkeley, August 2021.
• Colin Schmidt, "Extending Temporal-Vector Microarchitectures for Two-Dimensional Computations", Ph.D. Thesis, University of California, Berkeley, August 2021.
• Albert Magyar, "Improving FPGA Simulation Capacity with Automatic Resource Multi-Threading", Ph.D. Thesis, University of California, Berkeley, May 2021.
• David Biancolin, "Automated, FPGA-Based Hardware Emulation of Dynamic Frequency Scaling", Ph.D. Thesis, University of California, Berkeley, May 2021.
• Ameer Haj-Ali, "Machine Learning in Compiler Optimization", Ph.D. Thesis, University of California, Berkeley, December 2020. PDF
• Eric Love, "Compiling Communication-Minimizing Query Plans", Ph.D. Thesis, University of California, Berkeley, December 2019. PDF
• Adam Izraelevitz, "Unlocking Design Reuse with Hardware Compiler Frameworks", Ph.D. Thesis, University of California, Berkeley, December 2019. PDF
• Donggyu Kim, "FPGA-Accelerated Evaluation and Verification of RTL Designs", Ph.D. Thesis, University of California, Berkeley, May 2019. PDF
• Martin Maas, "Hardware and Software Support for Managed-Language Workloads in Data Centers", Ph.D. Thesis, University of California, Berkeley, December 2017. PDF
• Chris Celio, "A Highly Productive Implementation of an Out-of-Order Processor Generator", Ph.D. Thesis, University of California, Berkeley, December 2017. PDF
• Ben Keller, "Energy-Efficient System Design Through Adaptive Voltage Scaling", Ph.D. Thesis, University of California, Berkeley, December 2017. PDF
• Scott Beamer, "Understanding and Improving Graph Algorithm Performance", Ph.D. Thesis, University of California, Berkeley, September 2016. PDF
  Winner of SPEC Kaivalya Dixit Distinguished Dissertation Award 2016
• Yunsup Lee, "Decoupled Vector-Fetch Architecture with a Scalarizing Compiler", Ph.D. Thesis, University of California, Berkeley, May 2016. PDF
• Henry Cook, "Productive Design of Extensible On-Chip Memory Hierarchies", Ph.D. Thesis, University of California, Berkeley, May 2016. PDF
• Andrew S. Waterman, "Design of the RISC-V Instruction Set Architecture", Ph.D. Thesis, University of California, Berkeley, January 2016. PDF
• Brian Zimmer, "Resilient Design Techniques for Improving Cache Energy Efficiency", Ph.D. Thesis, University of California, Berkeley, August 2015.
• Sarah Bird, "Optimizing Resource Allocations for Dynamic Interactive Applications", Ph.D. Thesis, University of California, Berkeley, May 2014. PDF
• Zhangxi Tan, "Using FPGAs to Simulate Novel Datacenter Network Architectures at Scale", Ph.D. Thesis, University of California, Berkeley, June 2013. PDF
• Heidi Pan, "Cooperative Hierarchical Resource Management for Efficient Composition of Parallel Software", Ph.D. Thesis, Massachusetts Institute of Technology, June 2010. PDF
• Christopher F. Batten, "Simplified Vector-Thread Architectures for Flexible and Efficient Data-Parallel Accelerators", Ph.D. Thesis, Massachusetts Institute of Technology, February 2010. PDF
• Jae W. Lee, "Globally Synchronized Frames for Guaranteed Quality-of-Service in Shared Memory Systems", Ph.D. Thesis, Massachusetts Institute of Technology, September 2009. PDF
• Mark J. Hampton, "Reducing Exception Management Overhead with Software Restart Markers", Ph.D. Thesis, Massachusetts Institute of Technology, February 2008. PDF
• Ronny Krashinsky, "Vector-Thread Architecture and Implementation", Ph.D. Thesis, Massachusetts Institute of Technology, May 2007. PDF
  Winner, George M. Sprowls Award for best Ph.D. thesis in Computer Science, MIT, 2007.
• Kenneth C. Barr, "Summarizing Multiprocessor Program Execution with Versatile, Microarchitecture-Independent Snapshots", Ph.D. Thesis, Massachusetts Institute of Technology, August 2006. PDF
• Jessica H. Tseng, "Banked Microarchitectures for Complexity-Effective Superscalar Microprocessors", Ph.D. Thesis, Massachusetts Institute of Technology, May 2006. PDF
• Albert Ma, "Circuits for High-Performance Low-Power VLSI Logic", Ph.D. Thesis, Massachusetts Institute of Technology, May 2006. PDF
• Michael Zhang, "Latency Reduction Techniques for Chip Multiprocessor Cache Systems", Ph.D. Thesis, Massachusetts Institute of Technology, January 2006. PDF
• Seongmoo Heo, "Optimal Digital System Design in Deep Submicron Technology", Ph.D. Thesis, Massachusetts Institute of Technology, January 2006. PDF
• Emmett Witchel, "Mondriaan Memory Protection", Ph.D. Thesis, Massachusetts Institute of Technology, February 2004. PDF
  Received Honorable Mention, ACM Distinguished Dissertation Awards, 2004.
  Winner, George M. Sprowls Award for best Ph.D. thesis in Computer Science, MIT, 2004.

Masters Theses Supervised

• Max Banister, "Low Overhead Remote Procedure Call System for Saturn DSP", M.S. Thesis, University of California, Berkeley, May 2022. PDF
• Zitao Fang, "LEM: A Configurable RISC-V Vector Unit Based on Parameterized Microcode Expander", M.S. Thesis, University of California, Berkeley, May 2022. PDF
• Xingyu Li, "Building Infrastructure Supporting High Performance FPGA-accelerated Chiplet Modeling", M.S. Thesis, University of California, Berkeley, May 2022. PDF
• Catherine Lu, "Dynamic Linking in Trusted Execution Environments in RISC-V", M.S. Thesis, University of California, Berkeley, May 2022. PDF
• Alex Thomas, "Enclaves in Real-Time Operating Systems", M.S. Thesis, University of California, Berkeley, May 2021. PDF
• Pranav Prakash, "End-to-end Model Inference and Training on Gemmini", M.S. Thesis, University of California, Berkeley, May 2021. PDF
• Ben Korpan, "RingBOOM: An Implementation of a Novel High-Performance Banked Microarchitecture", M.S. Thesis, University of California, Berkeley, August 2020. PDF
• Kyle Kovacs, "A Hardware Implementation of the Snappy Compression Algorithm", M.S. Thesis, University of California, Berkeley, May 2019. PDF
• Peijie Li, "Reduce Static Code Size and Improve RISC-V Compression", M.S. Thesis, University of California, Berkeley, May 2019. PDF
• Alon Amid, "Nested-Parallelism PageRank on RISC-V Vector Multi-Processors", M.S. Thesis, University of California, Berkeley, May 2019. PDF
• Jack Koenig, "A Hardware Accelerator for Computing an Exact Dot Product", M.S. Thesis, University of California, Berkeley, May 2018. PDF
• Palmer Dabbelt, "PLSI: A Portable VLSI Flow", M.S. Thesis, University of California, Berkeley, May 2017. PDF
• Donggyu Kim, "Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL ", M.S. Thesis, University of California, Berkeley, November 2016. PDF
• Albert Ou, "Mixed-Precision Vector Processors", M.S. Thesis, University of California, Berkeley, December 2015. PDF
• Ben Keller, "Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency", M.S. Thesis, University of California, Berkeley, December 2015. PDF
• Eric Love, "Ressort: An Auto-Tuning Framework for Parallel Shuffle Kernels", M.S. Thesis, University of California, Berkeley, December 2015. PDF
• Martin Maas, "PHANTOM: Practical Oblivious Computation in a Secure Processor", M.S. Thesis, University of California, Berkeley, May 2014. PDF
• Wenyu Tang, "Automatic Functional Datapath Optimization", M.S. Thesis, University of California, Berkeley, May 2014. PDF
• Huy Tran-Ba Vo, "Hardware Construction in Chisel" M.S. Thesis, University of California, Berkeley, May 2013. PDF
• Brian Zimmer, "Resilient Design Methodology for Energy-Efficient SRAM", M.S. Thesis, University of California, Berkeley, May 2012. PDF
• Rimas Avižienis, "The Case for User-Level Preemptive Scheduling to Support Multi-Rate Audio Applications for Multi-Core Processors", M.S. Thesis, University of California, Berkeley, December 2011. PDF
• Yunsup Lee, "Efficient VLSI Implementations of Vector-Thread Architectures", M.S. Thesis, University of California, Berkeley, December 2011. PDF
• Andrew S. Waterman, "Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed", M.S. Thesis, University of California, Berkeley, May 2011. PDF
• Yong-jin Kwon, "Parameterized DRAM Model", M.S. Thesis, University of California, Berkeley, May 2010. PDF
• Sarah Bird, "Software Knows Best: A Case for Hardware Transparency and Measurability", M.S. Thesis, University of California, Berkeley, May 2010. PDF
• Scott Beamer, "Designing Multisocket Systems with Silicon Photonics", M.S. Thesis, University of California, Berkeley, December 2009. PDF
• Henry M. Cook, "Virtualizing Local Stores", M.S. Thesis, University of California, Berkeley, December 2009. PDF
• Carrell D. Killebrew, "L2 Cache to Off-chip Memory Networks for Chip Multiprocessors", M.S. Thesis, University of California, Berkeley, May 2008. PDF
• Asif I. Khan, "Emulation of Microprocessor Memory Systems Using the RAMP Design Framework", S.M. Thesis, Massachusetts Institute of Technology, February 2008. PDF
• Elizabeth A. Basha, "Fast Fourier Transform on a 3D FPGA", S.M. Thesis, Massachusetts Institute of Technology, September 2005. PDF
• Vimal Bhalodia, "SCALE DRAM Subsystem Power Analysis", M.Eng. Thesis, Massachusetts Institute of Technology, September 2005. PDF
• Steven Gerding, "The Extreme Benchmark Suite: Measuring High-Performance Embedded Systems", S.M. Thesis, Massachusetts Institute of Technology, September 2005. PDF
• Rose F. Liu, "AXCIS: Rapid Processor Architectural Exploration using Canonical Instruction Segments", M.Eng. Thesis, Massachusetts Institute of Technology, September 2005. PDF
• Brian Pharris, "The SCALE DRAM Subsystem", M.Eng. Thesis, Massachusetts Institute of Technology, May 2004. PDF
• Sean Lie, "Hardware Support for Unbounded Transactional Memory", M.Eng. Thesis, Massachusetts Institute of Technology, May 2004. PDF
• Kelly Koskelin, "EProf: An Energy Profiler for the iPAQ", M.Eng. Thesis, Massachusetts Institute of Technology, February 2004. PDF
• Aaron Mihalik, "VISTA: A Visualization Tool for Computer Architects", M.Eng. Thesis, Massachusetts Institute of Technology, February 2004, PDF
• Tina Cheng, "Sieve: An XML-Based Structural Verilog Rules Check Tool". M.Eng. Thesis, Massachusetts Institute of Technology, August 2003. PDF
• Regina Sam , "ZOOM: A Performance-Energy Cache Simulator". M.Eng. Thesis, Massachusetts Institute of Technology, May 2003. PDF
• Sheetal Jain , "Low-Power Single-Precision IEEE Floating-Point Unit". M.Eng. Thesis, Massachusetts Institute of Technology, May 2003. PDF
• Elina Kamenetskaya, "Video over IP: An Example Reconfigurable Computing Application for a Handheld Device". M.Eng. Thesis, Massachusetts Institute of Technology, May 2003. PDF
• Kenneth C. Barr, "Energy Aware Lossless Data Compression". S.M. Thesis, Massachusetts Institute of Technology, September 2002. PDF
• Heidi Pan, "High-Performance Variable-Length Instruction Encodings". M.Eng. Thesis, Massachusetts Institute of Technology, May 2002. PDF
  Winner, Charles and Jennifer Johnson Award for best M.Eng. thesis in computer science, MIT, 2002.
• Mark Hampton, "Exposing Datapath Elements to Reduce Microprocessor Energy Consumption", S.M. Thesis, Massachusetts Institute of Technology, June 2001. PDF
• Ronny Krashinsky, "Microprocessor Energy Characterization and Optimization through Fast, Accurate, and Flexible Simulation", S.M. Thesis, Massachusetts Institute of Technology, May 2001. PDF
• Seongmoo Heo, "A Low-power 32-bit Datapath Design", S.M. Thesis, Massachusetts Institute of Technology, August 2000. PDF
• Gong Ke Shen, "A Procedural Layout Library in Java", M.Eng. Thesis, Massachusetts Institute of Technology, May 2000. PDF
• Jessica Tseng, "Energy-Efficient Register File Design", S.M. Thesis, Massachusetts Institute of Technology, December 1999. PDF
• Mukaya Panich, "Reducing Instruction Cache Energy Using Gated Wordlines", M.Eng. Thesis, Massachusetts Institute of Technology, August 1999. PDF