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Yogesh Singh Chauhan

 

Postdoc & BSIM Program Manager

Department of Electrical Engineering and

Computer Science

University of California Berkeley

 

Email: yogesh(AT)eecs[dot]berkeley{dot}edu

 

Yogesh Singh Chauhan received the B.E. from S.G.S.I.T.S. INDORE, India in the field of Electronics and Telecommunication Engineering in 2001 and M.Tech. from IIT KANPUR (Indian Institute of Technology KANPUR), India in the field of Microelectronics, VLSI and Display Technologies in 2003. He received the Ph.D. degree from EPFL, Lausanne, Switzerland in compact modeling of high voltage MOSFETs in supervision of Prof. A. M. Ionescu and Prof. M. Declercq. He worked in ST Microelectronics, Noida, India in 2003-2004 and in Compact Modeling Group of Semiconductor Research and Development Center at IBM, Bangalore, India in 2007-2010. He was a visiting researcher in Prof. Shunri Oda’s group at Tokyo Institute of Technology, Japan in 2010. 

 

He is currently working as postdoctoral fellow in supervision of Prof. Chenming Hu and Prof. Ali Niknejad in BSIM group at University of California, Berkeley. His interests include Modeling, Simulation and Characterization of Semiconductor Devices (Bulk/SOI MOSFET, MultiGate FET e.g. TriGate/FinFET/UTBSOI, Tunnel FET, Suspended Gate FET, High Voltage MOSFET - LDMOS/VDMOS/IGBT, HEMT etc.).

 

Books:

 

Title: POWER/HVMOS Devices Compact Modeling (contributed a chapter)

Editor: Wladyslaw Grabinski and Thomas Gneiting

 

Journal Publications:

 

1.     M. A. Karim, Y. S. Chauhan, S. Venugopalan, A. B. Sachid, D. D. Lu, B.-Y. Nguyen, O. Faynot, A. M. Niknejad and C. C. Hu, “Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs”, accepted in IEEE Electron Device Letters, 2012.

2.     S. Khandelwal, Y. S. Chauhan, D. D. Lu, S. Venugopalan, M. A. Karim, A. B. Sachid, B.-Y. Nguyen, O. Rozeau, O. Faynot, A. M. Niknejad and C. C. Hu, “BSIM-IMG: A Compact Model for Ultra-Thin Body SOI MOSFETs with Back-Gate Control”, accepted in IEEE Transactions on Electron Devices, 2012.

3.     Y. S. Chauhan, R. Gillon, M. Declercq, A. M. Ionescu, “Impact of Lateral Nonuniform Doping and Hot Carrier Injection on Capacitance Behavior of High Voltage MOSFETs”, IETE Technical Review, Vol. 25, Issue 5, pp. 244-250, Sept.-Oct 2008.

4.     A. Rusu, M. Mazza, Y. S. Chauhan and A. M. Ionescu, “Oscillator Based on Suspended Gate MOS Transistors”, Romanian Journal of Information Science and Technology, Vol. 11, No. 4, pp. 423-433, 2008.

5.     D. Tsamados, Y. S. Chauhan, C. Eggimann, K. Akarvardar, H.S. Philip Wong, and A. M. Ionescu, “Finite element analysis and analytical simulations of Suspended Gate-FET for ultra-low power inverters”, Solid State Electronics, Vol. 52, Issue 9, pp. 1374-1381, Sept. 2008.

6.     K. Akarvardar, H.S. Philip Wong, C. Eggimann, D. Tsamados, Y. S. Chauhan and, A. M. Ionescu, “Analytical Modeling of the Suspended-Gate FET and Design Insights for Low Power Logic”, IEEE Transactions on Electron Devices, Vol. 55, No. 1, pp. 48-59, Jan. 2008.

7.     Y. S. Chauhan, R. Gillon, B. Bakeroot, F. Krummenacher, M. Declercq, and A. M. Ionescu, “An EKV-based High Voltage MOSFET Model with improved mobility and drift model”, Solid State Electronics, Vol. 51, Issues 11-12, pp. 1581-1588, Nov.-Dec. 2007.

8.     Y. S. Chauhan, F. Krummenacher, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, “Compact Modeling of Lateral Non-uniform doping in High-Voltage MOSFETs”, IEEE Transactions on Electron Devices, Vol. 54, No. 6, pp. 1527-1539, June 2007.

9.     Y. S. Chauhan, C. Anghel, F. Krummenacher, C. Maier, R. Gillon, B. Bakeroot, B. Desoete, S. Frere, A. Baguenier Desormeaux, A. Sharma, M. Declercq, and A. M. Ionescu,"Scalable General High Voltage MOSFET Model inlcuding Quasi-Saturation and Self-Heating effect", Solid State Electronics, Vol. 50, Issues 11-12, pp. 1801-1813, Nov.-Dec. 2006.

10.  C. Anghel, B. Bakeroot, Y. S. Chauhan, R. Gillon, C. Maier, P. Moens, J. Doutreloigne, and A. M. Ionescu, "New Method for Threshold Voltage Extraction of High Voltage MOSFETs based on Gate-to-Drain Capacitance Measurement", IEEE Electron Device Letters, Vol. 27, No. 7, pp. 602-604, July 2006.

 

Conference/Workshop Publications:

 

1.     M.-A. Chalkiadaki, A. Mangla, C. C. Enz, Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Niknejad, C. Hu, “Evaluation of the BSIM6 Compact MOSFET Model’s Scalability in 40nm CMOS Technology”, IEEE European Solid-State Device Research Conference, Bordeaux, France, Sept. 2012.

2.     Y. S. Chauhan, S. Venugopalan, M. A. Karim, S. Khandelwal, N. Paydavosi, P. Thakur, A. M. Niknejad and C. C. Hu, “BSIM – Industry Standard Compact MOSFET Models”, IEEE European Solid-State Device Research Conference, Bordeaux, France, Sept. 2012.

3.     Y. S. Chauhan, M. A. Karim, S. Venugopalan, S. Khandelwal, P. Thakur, N. Paydavosi, A. B. Sachid, A. Niknejad and C. Hu, “BSIM6: Symmetric Bulk MOSFET Model”, Workshop on Compact Modeling, Santa Clara, USA, June 2012.

4.     S. Khandelwal, Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad and C. Hu, “Analytical Surface Potential Calculation in UTBSOI MOSFET with Independent Back-Gate Control”, Workshop on Compact Modeling, Santa Clara, USA, June 2012.

5.     S. Khandelwal, Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad and C. Hu, “Analysis and Modeling of Vertical Non-uniform Doping in Bulk MOSFETs for Circuit Simulations”, IEEE International Caribbean Conference on Devices, Circuits and Systems, Playa del Carmen, Mexico, March 2012.

6.     S. Venugopalan, Y. S. Chauhan, D. D. Lu, M. A. Karim, A. M. Niknejad and C. Hu, “Modeling Intrinsic and Extrinsic Asymmetry of 3D Cylindrical Gate/ Gate-All-Around FETs for Circuit Simulations”, IEEE Non-Volatile Memory Technology Symposium, Shanghai, China, Nov. 2011.

7.     Y. S. Chauhan, D. D. Lu, S. Venugopalan, M. A. Karim, A. Niknejad and C. Hu, “Compact Models for sub-22nm MOSFETs”, Workshop on Compact Modeling, Boston, USA, June 2011.

8.     M. A. Karim, S. Venugopalan, Y. S. Chauhan, D. Lu, A. Niknejad and C. Hu, “Drain Induced Barrier Lowering (DIBL) Effect on the Intrinsic Capacitances of Nano-Scale MOSFETs”, Workshop on Compact Modeling, Boston, USA, June 2011.

9.     S. Parthasarathy, A. Trivedi, S. Sirohi, R. Groves, M. Carroll, D. Kerr, A. Tombak, P. Mason and Y. S. Chauhan, “RF SOI Switch FET Design and Modeling tradeoffs for GSM Applications”, IEEE International Conference on VLSI Design, Bangalore, India, Jan. 2010.

10.  Y. S. Chauhan, D. Tsamados, N. Abele, C. Eggimann, M. Declercq, and A. M. Ionescu, "Compact Modeling of Suspended Gate FET", IEEE International Conference on VLSI Design, Hyderabad, India, Jan. 2008. (Received Honorable Mention Award)

11.  A. Rusu, M. Mazza, Y. S. Chauhan, A. M. Ionescu, “MHz Oscillator based on Vibrating Gate MOS Transistor”, IEEE International Semiconductor Conference, Sinaia, Romania, Oct. 2007.

12.  D. Tsamados, Y. S. Chauhan, C. Eggimann, K. Akarvardar, H.S. Philip Wong, and A. M. Ionescu, “Numerical and analytical simulations of Suspended Gate – FET for ultra-low power inverters”, IEEE European Solid-State Device Research Conference, Munich, Germany, Sept. 2007.

13.  Y. S. Chauhan, R. Gillon, M. Declercq, and A. M. Ionescu, “Impact of Lateral Non-uniform doping and hot carrier degradation on Capacitance behavior of High Voltage MOSFETs”, IEEE European Solid-State Device Research Conference, Munich, Germany, Sept. 2007.

14.  K. Akarvardar, C. Eggimann, D. Tsamados, Y. Chauhan, A. M. Ionescu and, H.S. Philip Wong, “Analytical Modeling of the Suspended-Gate FET and Design Insights for Digital Logic”, IEEE Device Research Conference, Bend, USA, June 2007.

15.  W. Grabinski, T. Grasser, G. Gildenblat, G. Smit, M. Bucher, A. C. T. Aarts, A. Tajic, Y. S. Chauhan, A. Napieralski, T. A. Fjeldly, B. Iniguez, G. Iannaccone, M. Kayal, W. Posch, G. Wachutka, F. Pregaldiny, C. Lallement, L. Lemaitre, "MOS-AK: Open Compact Modeling Forum", International Workshop on Compact Modeling, Yokohama, Japan, Jan. 2007.

16.  Y. S. Chauhan, F. Krummenacher, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, "A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling", IEEE International Conference on VLSI Design, Banglore, India, Jan. 2007.

17.  Y. S. Chauhan, F. Krummenacher, C. Anghel, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, "Analysis and Modeling of Lateral Non-Uniform Doping in High-Voltage MOSFETs", IEEE International Electron Devices Meeting, San Francisco, USA, Dec. 2006.

18.  A. S. Roy, Y. S. Chauhan, C. C. Enz, J.-M. Sallesse, "Noise Modeling in Lateral Asymmetric MOSFET", IEEE International Electron Devices Meeting, San Francisco, USA, Dec. 2006.

19.  Y. S. Chauhan, C. Anghel, F. Krummenacher, A. M. Ionescu, M. Declercq, R. Gillon, S. Frere, and B. Desoete,"A Highly Scalable High Voltage MOSFET Model", IEEE European Solid-State Device Research Conference, Montreux, Switzerland, Sept. 2006.

20.  A. S. Roy, Y. S. Chauhan, J.-M. Sallesse, C. C. Enz, A. M. Ionescu, and M. Declercq, "Partitioning Scheme in the Lateral Asymmetric MOST", IEEE European Solid-State Device Research Conference, Montreux, Switzerland, Sept. 2006.

21.  Y. S. Chauhan, C. Anghel, F. Krummenacher, R. Gillon, A. Baguenier, B. Desoete, S. Frere, A. M. Ionescu and M. Declercq, "A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor", IEEE International Symposium on Quality Electronic Design, San Jose, USA, March 2006.

22.  C. Anghel, Y. S. Chauhan, N. Hefyene and A. M. Ionescu, "A Physical Analysis of High Voltage MOSFET Capacitance Behaviour", IEEE International Symposium on Industrial Electronics, Dubrovnik, Croatia, June 2005.

23.  B. Mazhari, Y. S. Chauhan, "Design of current-Programmed amorphous-Silicon AMOLED  Pixel Circuit", The 8th Asian Symposium on Information Display, China, 2003.

24.  B. Mazhari, Y. S. Chauhan, "A New Negative Feedback based poly-Silicon AMOLED Pixel Circuit with Highly Linear Transfer Characteristics", 10th International Display Workshop, Fukuoka, Japan, 2003. 

 

Presentations:

 

1.     Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, P. Thakur, N. Paydavosi, A. Niknejad, C. Hu, “BSIM Models: From Multi-Gate to the Symmetric BSIM6”, International Workshop on Device Modeling for Microsystems, Noida, March 2012.

2.     Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, P. Thakur, N. Paydavosi, A. Niknejad, C. Hu, W. wu, K. Dandu, K. Green, T. Krakowsky, G. Coram, S. Cherepko, S. Sirohi, A. Dutta, R. Williams, J. Watts, M.-A. Chalkiadakim A. Mangla, A. Bazigos, W. Grabinski, C. Enz, “Transitioning from BSIM4 to BSIM6”, International Workshop on Device Modeling for Microsystems, Noida, March 2012.

3.     Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad, C. Hu, W. wu, K. Dandu, K. Green, G. Coram, S. Cherepko, J. Wang, S. Sirohi, J. Watts, M.-A. Chalkiadakim A. Mangla, A. Bazigos, F. Krummenacher, W. Grabinski, C. Enz, “BSIM6: Symmetric Bulk MOSFET Model”, The Nano-Terra Workshop on the next generation MOSFET Compact Models, Lausanne, Switzerland, Dec. 2011.

4.     M. A. Karim, Y. S. Chauhan, S. Venugopalan, A. Niknejad, C. Hu, “BSIM-IMG: Surface Potential based UTBSOI MOSFET Model”, The Nano-Terra Workshop on the next generation MOSFET Compact Models, Lausanne, Switzerland, Dec. 2011.

5.     S. Venugopalan, Y. S. Chauhan, M. A. Karim, A. Niknejad, C. Hu, “BSIM-CMG: Advanced FinFET Model”, The Nano-Terra Workshop on the next generation MOSFET Compact Models, Lausanne, Switzerland, Dec. 2011.

6.     A. B. Sachid, Y. S. Chauhan and C. Hu, “Exploring Next-Generation FinFET Architectures for SRAM Applications”, MOS-AK Workshop, Washington DC, USA, Dec. 2011.

7.     Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad and C. Hu, “BSIM6: Next generation RF MOSFET Model”, MOS-AK Workshop, Washington DC, USA, Dec. 2011.

8.     D. Lu, S. Venugopalan, T. Morshed, Y. S. Chauhan, C-H Lin, M. Dunga, A. Niknejad and C. Hu, “A Multi-Gate CMOS Compact Model - BSIMMG MOS-AK Workshop, San Francisco, USA, Dec. 2010.

9.     Y. S. Chauhan, F. Krummenacher, C. Anghel, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, “A Compact Model for Circuit Simulation of High Voltage Lateral & Vertical DMOS Transistors”, ROBUSPIC Power Device Workshop, Napoli, Italy, June 2006.

10.  Y. S. Chauhan, F. Krummenacher, C. Anghel, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, “The HV-EKV MOSFET Model”, Compact Model Council meeting, Boston, USA, May 2006.