Parallel Timing Simulation on a Distributed Memory
Multiprocessor

Chih-Po Wen and Katherine A. Yelick

We present a parallel timing simulator, PARSWEC, that exploits
speculative parallelism and runs on a distributed memory
multiprocessor. It is based on an event-driven timing simulator
called SWEC.  Our approach uses optimistic scheduling to take
advantage of the latency of digital signals.  Using data from
trace-driven analysis, we demonstrate that optimistic scheduling
exploits more parallelism than conservative scheduling for
circuits with feedback signal paths.  We then describe the
PARSWEC implementation and discuss several design trade-offs.
Speedups over SWEC on large circuits are as high as 55 on a
64-node CM5 multiprocessor. These results indicate the
feasibility of using distributed memory multiprocessors for
large-scale circuit simulation.