I am currently a Founding Engineer at Pure Storage. I received my PhD from UC Berkeley in 2013. I was in the Parlab and ASPIRE project. Outside Pure, I spend my spare cycles helping the FireBox project. My research interests include large-scale computer and network systems, datacenter interconnect and storage system designs, computer architecture, massive-scale architecture simulation using FPGAs, and datacenter HW/SW co-design.
Email: xtan at cs dot berkeley dot edu
After finishing my PhD, I joined Pure Storage in a stealth team working on the FlashBlade product. FlashBlade is an all-flash rack-scale storage platform designed to store the biggest, the fastest unstructured data of today and tomorrow. FlashBlade is an elastic scale-out system that delivers all-flash performance to multi-petabyte-scale data sets at economics of less than $1/GB usable. It is a true co-designed hardware/software system, which scales flash storage from 90TB usable to over 1.6PB usable in only 4 Rack Units. Performance is outstanding at 15GB/s. Energy consumption is less than 1,800 Watt at peak load. The technology has been validated by real customers, such as the Mercedes AMG Formula 1 team, Shutterfly, MentorGraphics and etc. I am one of the early engineers designing and architecting the product.
View my talk at Berkeley for more details.
Traditional computer architecture research is incremental and boring. Building computer systems is an integral part of my research, as it is one of the best ways to valid assumptions. FPGAs are very interesting devices to implement architecture ideas, and run full software stacks. Againsting conventional wisdoms, we use FPGAs in an innovative way to look at large-scale full-system problems that could not be seen with traditional simulations.
I built a cluster using 24 Xilinx Virtex 5 FPGAs, simulating a 3,000-node datacenter with a runtime-configurable interconnect. Each simulated server runs the full Linux operating system and unmodified production software such as memcached. DIABLO is a full-custom FPGA design based on RAMP Gold. Using DIABLO, we have successfully reproduced the memcached request latency long tail with 2,000 simulated nodes. To the best of our knowledge, DIABLO is the world's largest execution-driven datacenter simulator, and it works!
DIABLO is my PhD thesis research project. I built all hardware components from scratch myself, including a mulithreaded SPARC processor, switch/NIC, and memory/SERDES controllers. Throughout the process, we have developed the taxonomy of FPGA Architecture Model Execution (FAME), which systematically defines the foundation for architecture simulations using FPGAs.
RAMP Gold allows rapid early design-space exploration of manycore systems. The RAMP Gold prototype runs on a single Xilinx Virtex-5 FPGA board and simulates a 64-core shared-memory target machine. We evaluate its performance using a modern parallel benchmark suite running on our manycore research operating system, achieving two orders of magnitude speedup compared to a widely-used software-based architecture simulator.
RAMP Gold is an open source project that has been downloaded for over 1,900 times since March 2010. It is currently used as a template design and a showcase for Systemverilog product development at Xilinx.
I worked with Chuck Thacker, John Davis, Fang Yu, Lintao Zhang on several research projects using FPGAs, including building a novel circuit-switching datacenter interconnect and a parallel SAT solver accelerator(PSAT)