Andrew S. Waterman

waterman@eecs.what_you'd_expect.edu

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I'm broadly interested in computer architecture and VLSI design. As of late, my research focus has been on the hardware-software interface. My Ph.D. thesis describes the design of RISC-V, a free and open instruction set architecture. We've fabricated several chips that contain RISC-V microprocessors, including [Nature 528 VLSI'15 ESSCIRC'14].

My M.S. thesis evaluates a variable-length instruction encoding of RISC-V, called RVC.

I have contribued to Akaros, an open-source operating system for manycore architectures. [HotPar'10]

I helped build RAMP Gold, an FPGA-hosted manycore emulator. [ISCA'10 DAC'10]

The Roofline Model is an insightful visual performance model for floating-point kernels.