I'm broadly interested in computer architecture and VLSI design. As of late, my research focus has been on the hardware-software interface. My Ph.D. thesis describes the design of RISC-V, a free and open instruction set architecture. We've fabricated several chips that contain RISC-V microprocessors, including [Nature 528 VLSI'15 ESSCIRC'14].
My M.S. thesis evaluates a variable-length instruction encoding of RISC-V, called RVC.
The Roofline Model is an insightful visual performance model for floating-point kernels.