Modeling and Verifying Circuits Using Generalized Relative Timing

Sanjit A. Seshia, Randal E. Bryant, and Kenneth S. Stevens. Modeling and Verifying Circuits Using Generalized Relative Timing. In 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pp. 98–108, IEEE Computer Society, March 2005.

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BibTeX

@inproceedings{seshia-async05,
  author    = {Sanjit A. Seshia and
               Randal E. Bryant and
               Kenneth S. Stevens},
  title     = {Modeling and Verifying Circuits Using Generalized Relative
               Timing},
  booktitle     = {11th International Symposium on Advanced Research in Asynchronous
               Circuits and Systems (ASYNC)},
  publisher = {IEEE Computer Society},
  year      = {2005},
  month = {March},
  pages     = {98--108},
}