Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits

Daniel E. Holcomb, Wenchao Li, and Sanjit A. Seshia. Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp. 785–790, April 2009.

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Abstract

Soft errors in combinational and sequential elements of digitalcircuits are an increasing concern as a result of technologyscaling. Several techniques for gate and latch hardeninghave been proposed to synthesize circuits that are tolerantto soft errors. However, each such technique has associatedoverheads of power, area, and performance. In this paper,we present a new methodology to compute the failures intime (FIT) rate of a sequential circuit where the failures are atthe system-level. System-level failures are detected by monitorsderived from functional specifications. Our approach includesefficient methods to compute the FIT rate of combinationalcircuits (CFIT), incorporating effects of logical, timing,and electrical masking. The contribution of circuit componentsto the FIT rate of the overall circuit can be computed from theCFIT and probabilities of system-level failure due to soft errorsin those elements. Designers can use this information toperform Pareto-optimal hardening of selected sequential andcombinational components against soft errors. We present experimentalresults demonstrating that our analysis is efficient,accurate, and provides data that can be used to synthesize alow-overhead, low-FIT sequential circuit.

BibTeX

@inproceedings{holcomb-date09,
 author = {Daniel E. Holcomb and Wenchao Li and Sanjit A. Seshia},
 title = {Design as You See {FIT}: System-Level Soft Error Analysis of Sequential Circuits},
 booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe (DATE)},
 pages = "785--790",
 month = "April",
 year = {2009},
 abstract = {Soft errors in combinational and sequential elements of digital
circuits are an increasing concern as a result of technology
scaling. Several techniques for gate and latch hardening
have been proposed to synthesize circuits that are tolerant
to soft errors. However, each such technique has associated
overheads of power, area, and performance. In this paper,
we present a new methodology to compute the failures in
time (FIT) rate of a sequential circuit where the failures are at
the system-level. System-level failures are detected by monitors
derived from functional specifications. Our approach includes
efficient methods to compute the FIT rate of combinational
circuits (CFIT), incorporating effects of logical, timing,
and electrical masking. The contribution of circuit components
to the FIT rate of the overall circuit can be computed from the
CFIT and probabilities of system-level failure due to soft errors
in those elements. Designers can use this information to
perform Pareto-optimal hardening of selected sequential and
combinational components against soft errors. We present experimental
results demonstrating that our analysis is efficient,
accurate, and provides data that can be used to synthesize a
low-overhead, low-FIT sequential circuit.},
}