Electrical Engineering and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

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Alan Jay Smith

Professor

Ph.D., Stanford University
S.B., MIT


Areas of Interest

Computer Architecture and Engineering
Operating Systems
Computer System Performance Analysis
Computer I/O Systems
Cache Memories
Memory Systems

Awards/Honors/Lectureships

  • Fellow of the IEEE, 1988
  • Fellow of the ACM, 2000
  • Fellow of the American Association for the Advancement of Science, 2001
  • A. A. Michelson Award of the Computer Measurement Group (CMG), 2003.
    The award is given as a lifetime achievement award for making
    significant, lasting contributions to the field of computer
    measurement and performance.
  • Harry Goode Award of the IEEE Computer Society, 2006, for outstanding
    contribution to the information processing field, citation reads:
    "For leadership in the measurement and evaluation of cache and memory
    system performance."
  • IEEE Reynold B. Johnson Information Storage Systems Award, for 2008,
    citation reads: "For contributions to the performance analysis of computer
    storage systems, including improvements to disk caches, prefetching
    and data placement."
  • IEEE Golden Core (Charter Member- 1996)
  • Best Paper Award, IEETC, 1979
  • ACM National Lecturer, 1985-1986
  • IEEE Distinguished Visitor, 1986-1987

Selected Professional Activities

  • Subject Area Editor, Journal of Parallel and Distributed Computing,
    February, 1989 - present.
  • Member, Editorial Board, Microprocessor Report, 2005-2007.
  • Member, IFIP Working Group 7.3, Computer System Modelling, January, 1989-
    present.
  • Executive Committee, IEEE Technical Committee on Microprocessors
    and Microsystems (TCMM), 1996-present.
  • Steering Committee, Hot Chips and Hot Interconnects, 1996-present,
    Chairman, 2001-present.
  • Chairman, ACM Special Interest Group on Computer Architecture (SIGARCH),
    July, 1991-June, 1993.
  • Chairman, ACM Special Interest Group on Operating Systems (SIGOPS).
    July 1983-June, 1987.
  • Board of Directors of SIGMETRICS (ACM Special Interest
    Group on Measurement and Evaluation), July, 1985-June, 1989.
  • Associate Editor, ACM Transactions on Computer Systems, August,
    1982 - December, 1993.
  • Chairman, Program Committee, Sigmetrics89 and Performance89, May, 1989,
    Berkeley, CA.
  • (Co-)Chairman, Program Committee, 2'nd (1990), 6'th (1994),
    9'th (1997), 17'th (2005) Hot Chips Symposia.
  • Member of the SDIO Panel on Computing in Support of Battle Management,
    ("Eastport Group"), summer, 1985.
  • Member, IEEE Futurebus (P896) Committee, 1985-1989.
    Member, Caching Working Group (P896.2)

Selected Publications

Refereed Journal Publications

  • "A Linear Time Two Tape Merge", (with R.W. Floyd), Information Processing Letters, 2, 1974, pp. 125-127.
  • "Interference in Multiprocessor Computer Systems with Interleaved Memory", (with F. Baskett), Communications of the ACM, 19, 6, June, 1976, pp. 327-334.
  • "Comments on a Paper by T. C. Chen and I. T. Ho", Communications of the ACM, 18, 8, August, 1976, p. 463.
  • "A Modified Working Set Paging Algorithm", IEEE Transactions on Computers, C-25, 9, September, 1976, pp. 907-914.
  • "Analysis of the Optimal, Look-Ahead, Demand Paging Algorithms", SIAM Journal on Computing, 5, 4, December, 1976, pp. 743-757.
  • "Two Methods for the Efficient Analysis of Memory Address Trace Data", IEEE Transactions on Software Engineering, SE-3, 1, January, 1977, pp. 94-101.
  • "Multiprocessor Memory Organization and Memory Interference", Communications of the ACM, 20, 10, October, 1977, pp. 754-761.
  • "A Comparative Study of Set Associative Memory Mapping Algorithms and Their Use for Cache and Main Memory", IEEE Transactions on Software Engineering, SE-4, 2, March, 1978, pp. 121-130.
  • "Sequentiality and Prefetching in Data Base Systems", ACM Transactions on Data Base Systems, 3, 3, September, 1978, pp. 223-247.
  • "Sequential Program Prefetching in Memory Hierarchies", IEEE Computer, 11, 12, December, 1978, pp. 7-21.
  • "Characterizing the Storage Process and its Effect on the Update of Main
    Memory by Write-Through", Journal of the ACM, 26, 1, January, 1979, pp. 6-27.
  • "An Analytic and Experimental Study of Multiple Channel Controllers", IEEE Transactions on Computers, C-28, 1, January, 1979, pp. 38-49. Winner, IEEE Best Paper award for best paper, IEEE Transactions on Computers, 1979.
  • "Multiprogramming and Memory Contention", Software - Practice and Experience, 10, 7, July, 1980, pp. 531-552.
  • "Internal Scheduling and Memory Contention", IEEE Transactions on Software Engineering, SE-7, 1, January, 1981, pp. 135-146.
  • "Analysis of Long Term File Reference Patterns for Application to File Migration Algorithms", IEEE Transactions on Software Engineering, SE-7, 4, July, 1981, pp. 403-417.
  • "Input/Output Optimization and Disk Architecture: A Survey", Performance Evaluation, 1, 2, 1981, pp. 104-117.
  • "Long Term File Migration: Development and Evaluation of Algorithms", Communications of the ACM, 24, 8, August, 1981, pp. 521-532.
  • "Optimization of I/O Systems by Cache Disk and File Migration: A Summary", Performance Evaluation, 1, 3, 1981, pp. 249-262.
  • "Cache Memories", Computing Surveys, 14, 3, September, 1982, pp. 473-530.
  • "Analysis of Branch Prediction Strategies and Branch Target Buffer Design", (with J. K. Lee), IEEE Computer, 17, 1, January, 1984, pp. 6-22.
  • "Disk Cache - Miss Ratio Analysis and Design Considerations", ACM Transactions on Computer Systems, 3, 3, August, 1985, pp. 161-203. See also ``Remark on Disk Cache - Miss Ratio Analysis and Design Considerations'', ACM TOCS, 5, 1, February, 1987, p. 93.
  • "Line (Block) Size Selection in CPU Cache Memories", IEEE Transactions on Computers, C-36, 9, September, 1987, pp. 1063-1075. (See correction IEEETC, 38, 6, June, 1989, p. 927.)
  • "Cache Memory Design: An Evolving Art", IEEE Spectrum, 24, 12, December, 1987, pp. 40-44. Translated to Japanese and republished in the Japanese version of IEEE Spectrum, vol 1. no. 7, August, 1988, pp. 25-32.
  • "The Fairchild CLIPPER: Instruction Set Architecture and Processor Implementation'' (with Walter Hollingsworth and Howard Sachs), Communications of the ACM, 32, 2, February, 1989, pp. 200-219. Republished in ``Reduced Instruction Set Computers'', 2'nd Edition, IEEE Computer Society Press Tutorial, 1990, pp. 239-258.
  • "Efficient (Stack) Algorithms for Analysis of Write-Back and Sector Memories'', (with James G. Thompson), January, 1987.
    ACM Transactions on Computer Systems, 7, 1, February, 1989, pp. 78-116.
  • "Evaluating Associativity in CPU Caches", (with Mark D. Hill), IEEE Transactions on Computers, special issue on Performance
    Evaluation, December, 1989, 38, 12, pp. 1612-1630. Republished in "Readings in Computer Architecture", Morgan-Kaufman,
    Hill, Jouppi, and Sohi, 2000, pp. pp. 82-100.
  • "Machine Characterization Based on an Abstract High Level Language Machine'', (with Rafael Saavedra-Barrera and Eugene Miya), IEEE Transactions on Computers, special issue on Performance Evaluation, December, 1989, 38, 12, pp. 1659-1679.
  • "The Task of the Referee'', IEEE Computer, 23, 4, April, 1990, pp. 65-73.
  • "Reducing and Manipulating Complex Trace Data'', (with Herve Touati), Computer Science Division Technical Report UCB/CSD 89/546, December, 1989, Software Practice and Experience, 21, 6, June, 1991, pp. 639-655.
  • "Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing'', (with Siegel, Abraham, Bain, Batcher, Casavant, DeGroot, Dennis, Douglas, Feng, Goodman, Huang, Jordan, Jump, Smith, Snyder, Stone, Tuck, Wah), J. Parallel and Distributed Computing, 16, pp. 199-211, 1992.
  • "Branch Target Buffer Design and Optimization'', with (Chris Perleberg), IEEETC, 42, 4, April, 1993, pp. 396-412.
  • "Cache Performance of the SPEC Benchmark Suite'' (with Jeffrey Gee, Mark Hill, Dionisios Penvmatikatos), IEEE MICRO, 13, 4, August, 1993, pp. 17-27.
  • "Performance Characterization of Optimizing Compilers'', (with Rafael Saavedra-Barrera, IEEETSE), July, 1995, vol. 21, no. 7, pp. 615-628.
  • "Measuring Cache and TLB Performance and Their Effect on Benchmark Run Times'' (with Rafael H. Saavedra), IEEE TC, October, 1995, 44, 10, pp. 1223-1235.
  • "Analysis of Benchmark Characteristics and Benchmark Performance Prediction'', (with Rafael Saavedra-Barrera), December, 1992. ACM TOCS, 14, 4, November, 1996, pp. 344-384.
  • "Characterization of Contention in Real Relational Databases'' (with Vigyan Singhal), VLDB journal, 6, 1, February, 1997, pp. 40-52.
  • "Scheduling Techniques for Reducing Processor Energy Use in MacOS'', (with Jacob Lorch), ACM Wireless Networks (WINET) Journal, 3, 5, October, 1997, pp. 311-324.
  • "CPU Cache Prefetching: Timing Evaluation of Hardware Implementations'', (with John Tse), IEEETC, 47, 5, May, 1998, pp. 509-526.
  • "Software Strategies for Portable Computer Energy Management'', (with Jacob Lorch), IEEE Personal Computing Magazine, 5, 3, June, 1998, pp. 60-73.
  • "Energy Consumption of Apple Macintosh Computers'', (with Jacob Lorch), IEEE MICRO, 18, 6, November/December, 1998, pp. 54-63.
  • "Implementation Issues in Modern Cache Memories'', (with Jih-Kwon Peir and Windsor Hsu), IEEETC, 48, 2, February, 1999, pp. 100-110.
  • "Building VTrace, a Tracer for Windows NT" (with Jacob R. Lorch), Microsoft Systems Journal (MSDN Magazine), October, 2000, vol. 15, no. 10,pp. 86-102.
  • "Tracing Windows95", (with Min Zhou), Journal of Microprocessors and Microsystems, 24, 7, November 1, 2000, pp. 333-347.
  • "Analysis of the Characteristics of Production Database Workloads and Comparison with the TPC Benchmarks", (with Windsor Hsu and Honesty Young), IBM Systems Journal, 40, #3, 2001, pp. 781-802.
  • "I/O Reference Behavior of Production Database Workloads and the TPC Benchmarks - An Analysis at the Logical Level", (with Windsor Hsu and Honesty Young), ACM Transactions on Database Systems, 26, 1. March, 2001, pp. 96-143.
  • "Design and Characterization of the Berkeley Multimedia Workload", (with Nathan Slingerland), December 20, 2000, ACM Multimedia Systems Journal, 8, 4, 2002, pp. 315-327.
  • "Measuring the Performance of Multimedia Instruction Sets" (with Nathan Slingerland), IEEETC, 51, 11, November, 2002, pp. 1317-1332.
  • "Characteristics of I/O Traffic in Personal Computer and Server Workloads", (with Windsor W. Hsu) IBM Systems Journal, vol. 42, no. 2, 2003, pp. 347-372.
  • "The Performance Effect of I/O Optimizations and Disk Improvements," Windsor W. Hsu and Alan Jay Smith, IBM J. of Research
    and Development, 48, 2, March, 2004, pp. 255-289.
  • "PACE: A New Approach to Dynamic Voltage Scaling", (with Jacob Lorch), IEEETC, 53, 7, July, 2004, pp. 856-869.
  • "Multimedia Instruction Sets for General Purpose Microprocessors: A Survey" (with Nathan Slingerland), J. of Microprocessors and Microsystems, Vol 29/5, June, 2005, pp 225-246.
  • "The Automatic Improvement of Locality in Storage Systems," (with Windsor W. Hsu), ACM Transactions on Computer Systems, 23, 4, November, 2005, pp. 424-473.
  • "Workloads - Creation and Use", Communications of the ACM, 50, 11, November, 2007, pp. 45-50.

Refereed Conference Publications

  • "A Performance Analysis of Multiple Channel Controllers", Proc. 1'st Annual SIGME Symposium on Measurement and Evaluation,
    Palo Alto, Ca., February, 1973, pp. 37-46.
  • "A Locality Model for Disk Reference Patterns", Proc. IEEE Computer Society Conference (Compcon), February, l975, San Francisco, Ca., pp. 109-112.
  • "Analysis of a Locality Model for Disk Reference Patterns", Proc. Second Conference on Information Sciences and Systems,
    The John Hopkins University, Baltimore, Md., April, 1976, pp. 593-601.
  • "A Queueing Network Model for the Effect of Data Compression on System Efficiency", Proc. NCC, June, 1976, New York, New York, pp. 457-465.
  • "On the Effectiveness of Set Associative Page Mapping and its Application to Main Memory Management", Proc. Second International Conference on Software Engineering, San Francisco, Ca., October, 1976, pp. 286-292.
  • "On the Effectiveness of Buffered and Multiple Arm Disks", Proc. Fifth Computer Architecture Symposium, April, 1978, Palo Alto, Ca., pp. 242-248.
  • "Directions for Memory Hierarchies and Their Components: Research and Development", Proc. COMPSAC Conference, Chicago, Ill., November, 1978, pp. 704-709.
  • "Experimental Evaluation of On-Chip Microprocessor Cache Memories", (with Mark Hill), Proc. 11'th Annual Symposium on Computer Architecture, June, 1984, Ann Arbor, Michigan, pp. 158-166.
  • "Problems, Directions and Issues in Memory Hierarchies", Proc. 18'th Annual Hawaii International Conference on System Sciences, January 2-4, 1985, Honolulu, Hawaii, pp. 468-476.
  • "A File System Tracing Package for Berkeley Unix", (with Songnian Zhou and Herve DaCosta), Proc. 1985 USENIX Summer Conference, Portland, Oregon, (Hosted by University of Oregon), June 12-14, 1985, pp. 407-419.
  • "Cache Evaluation and the Impact of Workload Choice", Proc. 12'th International Symposium on Computer Architecture, June 17-19, 1985, Boston, Mass, pp. 64-75.
  • "CPU Cache Consistency with Software Support and Using `One Time Identifiers'", Proc. Pacific Computer Communication Symposium, Seoul, Republic of Korea, October 22-24, 1985, pp. 142-150. Available as UC Berkeley CS Division Technical Report UCB/CSD 86/290.
  • ``A Class of Compatible Cache Coherency Protocols and Their Support by the IEEE Futurebus'' (with Paul Sweazey), Proc. 13'th Ann. Int. Symp. on Computer Architecture, Tokyo, Japan, June, 1986, pp. 414-423.Republished in ``The Cache Coherence Problem in Shared Memory Multiprocessors: Hardware Solutions'', ed. Tomasevic and Milutinovic, IEEE Computer Society Press, 1993, pp. 228-237. Also republished in "Advanced Multi-Microprocessor Bus Architectures" , ed. Janusz Zalewski, IEEE Computer Society Press, August, 1994, pp. 261-270.
  • ``Design of CPU Cache Memories'', Proc. IEEE TENCON, Seoul, Korea, August, 1987 (Invited Paper), p. 30.2.1-30.2.10. Also available as Computer Science Division Technical Report UCB/CSD 87/357. Republished in ``The Cache Coherence Problem in Shared Memory Multiprocessors: Hardware Solutions'', ed. Tomasevic and Milutinovic, IEEE Computer Society Press, 1993, p. 4-13.
  • ``Memory Hierarchies: Research and Development'', Proc. Government Microcircuit Applications Conference (GOMAC), November, 1988, Las Vegas, Nevada, pp. 7-11.
  • ``The Performance Impact of Vector Caches'', (with Jeffrey Gee), Proc. 25'th Hawaii Intl. Conf. on System Sciences, January,
    1992, Hawaii, Volume I, pp. 437-448.
  • ``The Effectiveness of Caches for Vector Processors'', (with Jeffrey Gee), Proc. Int. Conf. on Supercomputing, Manchester, England, July 11-15, 1994, pp. 333-343.
  • ``Analysis of Multiprocessor Memory Reference Behavior'', (with Jeffrey Gee), Proc. ICCD'94 (IEEE Intl. Conf. on Computer Design: VLSI in Computers and Processors), Cambridge, MA, October 10-12, 1994, pp. 53-59.
  • ``The Need for Measured Data in Computer System Performance Analysis, or, Garbage In, Garbage Out,'' Proc. Compsac'94 (Eighteenth Annual Computer Software and Applications Conference), November 9-11, 1994, Taipei, Taiwan, pp. 426-431.
  • ``Evaluation of Cache Consistency Algorithm Performance'' (with Jeffrey Gee), Proc. Mascots'96 (Intl. Workshop on Modeling, Analysis and Simulation of Computer and Telecommunications Systems) Conference, pp. 236-249, February 1-3, 1996, San Jose, CA.
  • ``Reducing Processor Power Consumption by Improving Processor Time Management in a Single-User Operating System'', (with Jay Lorch), Proc. ACM/IEEE Mobicom Conference, November 10-12, 1996, Rye, NY, pp. 143-154.
  • ``Disk Caching in Large Database and Timeshared Systems'', (with Barbara Tockey Zivkov), Proc. Mascots'97 (Fifth Intl. Workshop on Modeling, Analysis and Simulation of Computer and Telecommunications Systems) Conference, Haifa, Israel, January, 1997, pp. 184-195.
  • ``Disk Cache Design and Performance as Evaluated in Large Timesharing and Database Systems'', (with Barbara Tockey Zivkov), Proc. CMG (Computer Measurement Group) Conference, December 7-12, 1997, Orlando, FL., pp. 639-658.
  • ``The Pool of Subsectors Cache Design'', (with Jeffrey Rothman), Proceedings, International Conf. on Supercomputing, Rhodes, Greece, June, 1999, pp. 31-42.
  • ``Multiprocessor Memory Reference Generation Using Cerberus'' (with Jeffrey Rothman), Proc. Seventh Intl. Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems (MASCOTS), October 24-28, 1999, University of Maryland, pp. 278-287.
  • "Analysis of Personal Computer Workloads", (with Min Zhou), Proc. Seventh Intl. Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems (MASCOTS), October 24-28, 1999, University of Maryland, pp. 208-217.
  • "Projecting the Performance of Decision Support Workloads on Systems with Smart Storage (SmartSTOR)", (with Windsor Hsu and Honesty Young), Proc. Seventh International Conference on Parallel and Distributed Systems, (ICPADS'2000), July 4 - 7, 2000, pp. 417-425, Iwate Prefectural University, Iwate, Japan.
  • "Analysis of Shared Memory Misses and Reference Patterns", (with Jeffrey Rothman), Proc. ICCD, 2000 (IEEE Intl. Conf. on Computer Design: VLSI In Computers), Austin, Texas, September 17-20, 2000, pp. 187-198.
  • "Sector Cache Design and Performance" (with Jeffrey Rothman), Proc. MASCOTS, 2000 (Eighth Intl. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems), August 29-September 1, 2000, pp. 124-133.
  • "Improving Dynamic Voltage Scaling Algorithms with PACE", (with Jay Lorch), Proc. Sigmetrics 2001/Performance 2001, June 16-20, 2001, Cambridge, MA, pp. 50-61.
  • "Cache Performance for Multimedia Applications" (with Nathan Slingerland), Proc. International Conf. on Supercomputing, Sorrento, Italy, June 17-21, 2001, pp. 204-217.
  • "Performance Analysis of Instruction Set Architecture Extensions for Multimedia", (with Nathan Slingerland), Proc. 3'rd Workshop on Media and Streaming Processors, Austin, Texas, December 2. 2001, pp. 53-75.
  • "Minerva: An Adaptive Subblock Coherence Protocol for Improved SMP Performance", (with Jeffrey Rothman), Proc. 4th International Symposium on High Performance Computing, Japan Atomic Energy Research Institute, Kansai Research Establishment, (JAERI-KRE), May 15-17, 2002, Kansai Science City, JAPAN, pp. 64-77. (Published it the "Lecture Notes in Computer Science" series, under the title "High Performance Computing", by Springer-Verlag.
  • "Operating System Modifications for Task-Based Speed and Voltage Scheduling", (with Jacob Lorch), Proc. MobiSys 2003, San Francisco, CA., May 5-8, 2003, pp. 215-230.
  • "Using User Interface Event Information in Dynamic Voltage Scaling Algorithms," (with Jacob Lorch), Proc. MASCOTS 2003, Orlando, Florida, October 12-15, 2003, pp. 46-55.
  • "WhoPay: A Scalable and Anonymous Payment System for Peer-to-Peer Environments," (with Kai Wei, Yih-Farn Chen, and Binh Vo), UC Berkeley Computer Science Technical Report CSD-5-1386, May, 2005, Proc. ICDCS 2006 (26'th Intl. Conf. on Distributed Systems, July 4-7, 2006, Lisbon, Portugal.)
  • "Efficient Search in File Sharing Networks," (with Paul Burstein), EECS Technical Report UCB/EECS-2006-179, December 16, 2006, (www.eecs.berkeley.edu/ Pubs/TechRpts/ 2006/EECS-2006-179.html). Proc. 13'th Intl. Conf. on Parallel and Distributed Systems, Hsinchu, Taiwan, December 5-7, 2007, paper #18.
  • "Power Consumption in a Real, Commercial Multimedia Core," Dominic Aldo Antonelli, Alan J. Smith and Jan-Willem van de Waerdt, Proc. Computing Frontiers 2009, May 18-20, 2009, Ischia, Italy. Expanded version: UC Berkeley EECS Technical Report UCB/EECS-2008-24, March 21, 2008, www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-24.html.

(Publications Last Updated April, 2009)
   

Contact Information

735 Soda Hall
tel: 510-642-5290
smith<at>eecs.berkeley.edu