Last First Email Area Partner
Agrawal Alok aloka@cs.Berkeley.edu Benchmarking Chu
Chen Jennie jennie@eecs.berkeley.ed Low Power, MH, or ILP
Chen Tzu-Yi tzuyi@cs.berkeley.edu DLX Instruction Scheduling Tabbara
Chenney Stephen schenney@cs.Berkeley.ed Arch Support for Virt Reality
Cho Franklin fscho@cory.berkeley.eduLow Power, ILP
Chu Michael mchu@cs.berkeley.edu Benchmarking Agrawal
Chun Brent bnc@cs.berkeley.edu Network, I/O, Mem Hierarchy
Fromm Richard rfromm@cs.berkeley.edu Instruction Level Parallelism
Galicia Geroncio galicia@cory.EECS.Berkeley.edu Mem System for Embedded Proc
Gauthier Paul gauthier@cs.berkeley.edu Xact Sys/Mem Hier or Compression
Harada Daishi daishi@cs.berkeley.edu Low Power/Networks Stemm
Jackson Trey trey@cs.Berkeley.edu
Jalnapurkar Sameer smj@math.berkeley.edu Hi Perf Networking/SP Design
McGaughy Bruce brucemcg@eecs.berkeley.EduEmbedded Processor Support
Mittal Alok alok@cs.Berkeley.edu Measurement/Benchmarking/LP
Nayak Ashwin ashwin@cs.berkeley.edu Special Purpose Architectures
Pfrommer Bernd pfrommer@physics.berkeley.edu Benchmarking/Scientific 3D FFT
Rajamani Sriram sriramr@ic.Berkeley.edu Special Purpose Architectures/Embedded
Reznik Anna annar@cory.Berkeley.edu Low Power Architecture
Reznik Dan dreznik@cs.berkeley.edu
Stemm Mark stemm@cs.berkeley.edu Low Power/Networks Harada
Su Zendong zhendong@cs.berkeley.edu Branch Prediction Zhou
Sutton Roy rsutton@eecs.berkeley.edu
Tabbara Bassam tbassam@cory.EECS.Berkeleye.edu DLX Instruction Scheduling Chen, Tzu-Yi
Tokuyasu Taku tokuyasu@cs.berkeley.edu Benchmarking/Scientific Pfrommer??
Viswanath Pramod pvi@cory.eecs.Berkeley.edu Special Purpose/Signal Processing
Wan Marlene marlene@zabriskie.eecs.edu
Warner Patrick pow@eecs.Berkeley.edu Network Memory/Network Galicia??
Wong Tina Han twong@cs.Berkeley.edu
Zege Andrey zege@saab.cs.Berkeley.edu
Zhou Min mzhou@eecs.berkeley.edu Branch Prediction Su