Computer Science 252. Graduate Computer Architecture
Homework Assigment #0.5, Due 1 September 95
Draw the block diagram of a direct mapped cache given the following specifications.
Be sure to indicate the sizes of the cache and tag stores in terms of bit or byte widths
and number of words. Show how the address is partitioned into pieces to access the various
subsystems of the cache.
- A word is 32-bits or 4 bytes.
- The cache is accessed by word; you need not support byte-oriented access.
- Addresses are 32-bits wide.
- The cache store should be organized to be 8 words/32 bytes wide.
- The cache is direct mapped.