Computer Science 150: Components and Design Techniques for Digital Systems (5 Units)

Spring 2004

Table of Contents

Catalog Description
Course Information
Course Staff
Course Calendar
Policies
Discussion

Catalog Description

CS 150. Components and Design Techniques for Digital Systems. (5) Three hours of lecture, one hour of discussion, and three hours of laboratory per week. Prerequisites: 61C, Electrical Engineering 40 or 42. Basic building blocks and design methods to contruct synchronous digital systems. Alternative representations for digital systems. Bipolar TTL vs. MOS implementation technologies. Standard logic (SSI, MSI) vs. programmable logic (PLD, PGA). Finite state machine design. Digital computer building blocks as case studies. Introduction to computer-aided design software. Formal hardware laboratories and substantial design project. Informal software laboratory periodically throughout semester. (F,SP) Katz, Newton, Pister.

Course Information

Course Goals
Course Syllabus
Introduction to modern digital logic design
Combinational logic
  • Switch logic and basic gates
  • Boolean algebra
  • Two-level logic
  • Regular logic structures
  • Multi-level networks and transformations
  • Programmable logic devices
  • Time response
  • Case studies
Sequential logic
  • Networks with feedback
  • Basic latches and flip-flops
  • Timing methodologies
  • Registers and counters
  • Programmable logic devices
  • Case studies
Finite state machine design
  • Concepts of FSMs
  • Basic design approach
  • Specification methods
  • State minimization
  • State encoding
  • FSM partitioning
  • Implementation of FSMs
  • Programmable logic devices
  • Case studies
Elements of computers
  • Arithmetic circuits
  • Arithmetic and logic units
  • Register and bus structures
  • Controllers/Sequencers
  • Microprogramming
Computer-aided design tools for logic design
  • Schematic entry
  • State diagram entry
  • Hardware description language entry
  • Compilation to logic networks
  • Simulation
  • Mapping to programmable logic devices
Practical topics
  • Non-gate logic
  • Asynchronous inputs and metastability
  • Memories: RAM and ROM
  • Implementation technologies
Course Times and Locations
Lecture: T, Th 2:00-3:30, 10 Evans. NOTE: Lectures will be Webcast.
Discussions: W 9:00-10:00, W 10:00-11:00 CANCELLED!, W 3:00-4:00, Th 9:00-10:00, Th 10:00-11:00; All discussions are held in 125 Cory! You may attend any discussion section.
Laboratory Lecture: F 2:00-3:00, 125 Cory.
Laboratories: M 9:00-12:00 CANCELLED!, M 5:00-8:00, Tu 11:00-2:00, W 11:00-2:00, W 5:00-8:00 (all in 125 Cory Hall)

Time

Monday

Tuesday

Wednesday

Thursday

Friday

0900

Lab 011

CANCELLED

Disc 101

125 Cory

Disc 104

125 Cory

0930

1000

Disc 102

CANCELLED

Disc 105

125 Cory

1030

1100

Lab 013

125 Cory

Lab 014

125 Cory

1130

1200

1230

1300

1330

1400

Lecture

10 Evans

Lecture

10 Evans

Lab Lecture

125 Cory

1430

1500

Disc 103

125 Cory

1530

1600

1630

1700

Lab 012

125 Cory

Lab 015

125 Cory

1730

1800

1830

1900

1930

Course Textbook
Required: R. H. Katz, G. Borriello, Contemporary Logic Design, 2nd Ed., Prentice Hall/Pearson Publishing, Upper Saddle River, NJ, 2004. Available in Draft Form and distributed through Copy Central on Hearst west of Euclid. Readings denoted by K&B.
Recommended: M. D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall/Pearson Publishing, Upper Saddle River, NJ, 2003. Required text from last semester. Lots more Verilog examples than K&B, but not very useful for lecture portion of course.
Course Grading

Course Staff

Course Instructor
Professor Randy H. Katz, Computer Science Division, EECS Department, 637 Soda Hall, 510-642-8778.
Office Hours: Tuesdays, 1-2 PM, W 9-10 AM, and by appointment. E-mail: randy@cs.Berkeley.edu
Teaching Assistants
Head TA: Greg Gibeling (gdgib@uclink.Berkeley.edu), office hours TBD, 125 Cory
Gabriel Eirea (geirea@eecs.Berkeley.edu), office hours TBD, 125 Cory
Eric Chung (e_chung@uclink.Berkeley.edu), office hours TBD, 125 Cory
Zohar Hyder (zhyder@eecs.Berkeley.edu), office hours TBD, 125 Cory
Michael Liao (mliao@uclink.berkeley.edu), office hours TBD, 125 Cory
Readers
To Be Determined

Course Calendar

Course Calendar, CS 150, Spring 2004

Week

Day

Topic

HW

Lab

1

20 Jan

Course Administration.
Logic Review: The Many Representations of Hardware.
Readings: K&B, Ch. 1; pp. 1-27.

Lec #1: Instrumentation

22 Jan

Transistor and Gate Logic.
Readings: K&B, Sec. 2.1, 2.3, 2.4; pp. 34-37, 46-66.

2

27 Jan

Combinational Logic.
Readings: K&B, Sec. 2.6, 3.5; pp. 77-81, 131-134.

Lab #1: Instrumentation

Lec #2: Cad Tool Flow

29 Jan

Programmable Logic: PAL/PLA and FPGA.
Readings: K&B, Sec. 4.1, 4.2, 4.3; pp. 157-209.

3

3 Feb

Verilog Hardware Description Language.
Readings: K&B, Sec. 3.6; pp. 143-148.

Lab #2: Cad Tool Flow

Lec #3: Verilog Simulation

5 Feb

Basic Finite State Machines: Flip-Flops, Registers, Shifters, Counters.
Readings: K&B, Sec. 6.1, 6.2.1-6.2.3, 6.3, 7.1; pp. 261-300, 310-324.

4

10 Feb

Moore and Mealy Machines.
Readings: K&B, Sec. 7.2, 7.3; pp. 324-342.

Lab #3: Verilog Simulation

Lec #4: Verilog Synthesis

12 Feb

FSM Synthesis, State Machine Timing.
Readings: K&B, Sec. 6.2, 7.4, 9.1, 9.2; pp. 280-285, 342-350, 409-417.

5

17 Feb

Midterm I Review

Lab #4: Verilog Synthesis

Lec #5: Debugging

19 Feb

Midterm I

6

24 Feb

Case Study: SDRAM/Memory Controller.
Readings: K&B, Sec. 10.4, 10.6; pp. 474-490, 495-508.

Lab #5: Debugging

Lec #6: Ckpt #1:
Memory Controller, I

26 Feb

Project Description: Multimedia Network Router.
Readings: Project specification documents.

7

2 Mar

Datapath Building Blocks: Arithmetic Units, Register Files, Shifters, FIFOs, Memories.
Readings: K&B, Sec.5.5-5.7, 6.3, 6.4; pp. 235-256, 289-299.

Lab: Ckpt #1: Memory
Controller (2 weeks)


Lec #7: Memory Controller, II

4 Mar

Datapath Interconnection: Point-to-Point, Single Bus, Mixed Strategy
Readings: K&B, Ch. 11.

8

9 Mar

Datapath Control: State Machines for Control; Register Transfer Abstraction.
Readings: K&B, Ch. 12.

Lab: Ckpt #1 Memory
Controller (Due)

Lec #8: Ckpt #2

11 Mar

Datapath Control: Microprogramming.
Readings: K&B, Ch. 12.

9

16 Mar

Control Timing, Pipelining, Re-timing.
Readings: K&B, Ch. 12;

Lab: Ckpt #2 (2 weeks)

Lec #9: Tips and Techniques

18 Mar

Midterm II Review

Spring Break

22-26 Mar


10

30 Mar

Midterm II

Lab: Ckpt #2 (Due)

Lec #10: Ckpt #3

1 Apr

State Machine Optimization, State Encodings, and State Assignment.
Readings: K&B, Sec. 7.4, 8.1, 8.2; pp. 342-350, 375-387.

11

6 Apr

State Machine Partitioning and Synchronous Inter-FSM Communications.
Readings: K&B, Sec. 8.3, 8.4; pp. 387-399.

Lab: Ckpt #3 (1 week)

Lec #11: Ckpt #4

8 Apr

Design for Test: Observation.

12

13 Apr

Design for Test: Self-Checking.

Lab: Ckpt #4 (1 week)


Lec #12: Final Integration

15 Apr

Metastability, Arbiter Design, Hazards.
Readings: K&B, Sec. 6.2.4, 6.2.5, 3.5.4-3.5.8; pp. 284-289, 134-141.

13

20 Apr

Asynchronous Communications.

Lab: Final Integration
(2 weeks)

22 Apr

Arithmetic Circuits: Building Blocks.
Readings: K&B, Sec. 5.6, 5.7; pp. 239-252.

14

27 Apr

Arithmetic Circuits: Combinational and Sequential Multiplier.
Readings: K&B, Sec. 5.8, 10.5; pp. 252-256, 490-495.

Lab: Final Integration
and Project Demonstration


Lec #13: Final Report Format

29 Apr

Evolution of FPGA Architectures.
Readings: K&B, Sec. 9.4, 9.5; pp. 428-454.

15

4 May

CPU Implementation I.
Readings: K&B, Ch. 12;

Lab: Final Report

6 May

CPU Implementation II.
Readings: K&B, Ch. 12;

15.5

11 May

Course Review


14 May

Final Exam, 12:30-3:30


Policies

Laboratory, Homework, and Examination Regrade Policies

Public Discussion

Technical Handouts


Page last updated 6 January 2004 by Randy Katz