EE 140 Final Project
Due Tuesday, 5/8/01, 5pm in 497 Cory Hall
Input: Variable capacitor, Cs=1pF +/- 5%
Output: Digital value proportional to the change in capacitance
Constraints:
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+/-2.5V supply with up to +10% variation
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maximum 1mW average power dissipation even at +10% supply voltage
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no ideal circuit components
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no explicit capacitors less than 10fF
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device models on the web
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1um minimum channel length for analog FETs, 0.5 um for switches
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1 accurate resistor
Report format
The report should be on 8.5x11 paper, stapled. Please do not bind
it, or put a fancy cover on it, or put it in a 3 ring binder. Just
a simple stapled stack of paper is fine.
There should be no spice decks or spice run output text in the report.
SPICE output plots would ideally be included as figures in-line with the
text, but individual pages
inserted are acceptable. I do not expect flowery prose, but I
do expect the report to have reasonable flow (and correct spelling and
grammar!).
Please use the following format for your report:
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Section 1: Introduction
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A- Overview - what did you try to do, and what did you succeed at doing
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B - block diagram of the design
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C - detailed timing diagram, including information on rise times, hold
times, and fall times for all signals
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Section 2: details of the circuit implementations
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A - design goals
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B - amplifier design(s) and performance
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operating point: currents, Vdsats, gain, bandwidth
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feedback analysis
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power consumption
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C - supply independent bias design and performance
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D - switch design(s) and performance
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settling time
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charge injection
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Section 3: ADC performance
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Demonstrate n-bits in time T, showing power consumption
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Explain any problems that you had. Showing results based on ideal
components is OK in this section to explain why things didn't work, but
make sure that they are *clearly* labeled in the figure caption and body
of the text.
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Section 4: Conclusion
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What did you try to do
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What did you succeed at doing
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What changes would you make in the future?
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How do speed, accuracy, and power consumption trade off in your design?
Could one of the three be improved at the sacrifice of another?
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Appendices:
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Hand calculations
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SPICE decks
Grading:
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Functional 4bit ADC with 10x pre-amplifier capable of 1kSample/second,
50%
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Each additional functional bit (up to 10 total): 5%
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Each additional factor of 10 in sample rate: 5%
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calculation of best and worst case charge injection and comparison to SPICE:
5%
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calculation of gain, unity gain freq, and phase margin of unity gain amplifier
(during reset) and comparison to SPICE: 5%
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Demonstrating that these transitions still work with up to a 10% increase
in supply voltage (to +/-2.75V): 10%
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Power consumption above 1mW cost your overall score 0.1% per microWatt
(or 100% of your score if you burn a total of 2mW).
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Late projects will be penalized 30% if turned in by 5pm wednesday 5/9/01,
and 60% if turned in by 5pm thursday 5/10/01.
Note: functionality of an n-bit ADC will be determined by showing inputs
that correspond to 0...00, 0..01, 01...1, 10...0, 1...10, 1...11 (1-bit
transitions at the bottom, middle, and top of the conversion range).
Note: your design is not *required* to have a 10x pre-amplifier, but
if you're just shooting for basic credit you need one.