# CS 294-4: Intelligent DRAM (IRAM)

## Background: What is a DRAM?

### Dynamic Random Access Memory

• Dynamic: it needs to be refreshed regularly or it loses its contents.
• Random Access: bits can access in any order with no penalty or (almost) no loss of performance.
• (Pictures in this lecture are copyrighted by Przybylski, who makes his living as a consultant, and thus are limited to Berkeley. Sorry.)

## 4Mb x 1 DRAM Block Diagram

The DRAM address is divided into rows and columns. (The address need not be divided as shown above, but it typically is in order to take advantage of spatial locality). Accessing any bit in DRAM given its row and column address is analogous to locating the bit in the memory array given its (x,y) coordinates.

The actual physical structure of DRAM differs from this (see next slides), but it is based on this fundamental logical structure.

## Storage Column

A single DRAM column contains a differential Sense Amplifier, column select, precharge circuitry, and a collection of Storage Cells. In a real DRAM there are actually several Bit Lines tied to each Sense Amp; typically there are 128 or 256 bits per Bit Line, and typically 4 or 8 Bit Lines are multiplexed to each Sense Amp. Each bit is a tiny capacitor that stores the value of the bit as a high (Vcc) or low (Gnd) voltage.

In a read operation, every bit in the selected row is moved to its respective Sense Amp. The selected column is then read out onto the I/O Line.

A detailed description follows:

1. The Precharge line for the desired Bit Line is turned on, equalizing the voltage on those Bit Lines to Vcc/2. Precharge is then turned off.
2. The desired Word Line and Bit Line Select (shown as Left Select and Right Select in the diagram) are turned on, allowing the contents of that Storage Cell to share its charge with its Bit Line. The voltage on that Bit Line will rise or fall slightly depending on the value stored in the Storage Cell.
3. The Sense Amp is turned on. It detects the minute voltage difference between the two Bit Lines and amplifies it. Since the Word Line is still on, the Sense Amp simultaneously reinforces the value stored in the Storage Cell.
4. The desired Column Select is turned on, causing the value to propagate out of the column on the I/O Lines. The Word Line, Bit Line Select, Sense Amp, and Column Select are then turned off.

### Writing

A write operation is similar. The value to be written is first fed into each Sense Amp over the I/O lines. The Sense Amp then writes this value into the selected Storage Cell. A detailed description follows:
1. The desired Column Select is turned on, allowing the write value to be to be copied from I/O Lines into the Sense Amp. The Sense Amp is then turned on, storing the value statically, and the Column Select is turned off.
2. The desired Word Line and Bit Line Select are turned on, causing the Sense Amp to drive its value into the selected Storage Cell. The Word Line and Bit Line Select are then turned off.

### Refreshing

Since capacitors are used as Storage Cells in a DRAM, the charge stored in each cell tends to leak away over time. Therefore it is necessary to refresh the value in each cell periodically. In typical DRAMs each row must be refreshed every 16, 32, 64, or 128 msec.

Refresing a row is similar to reading it, except the data does not emerge from the columns. Note that in the read operation above, the data in each Storage Cell is refreshed as a side-effect of reading it. In a refresh operation each bit in the selected row is moved to its respective Sense Amp. Each Sense Amp then amplifies the value on its Bit Lines and drives the refreshed value back into the Storage Cell.

## DRAM Read Operation Timing Diagram

This timing diagram shows the timing for the read operation described above.

1. Precharge is turned on, equalizing the Bit Lines voltages.
2. Precharge is turned off.
3. Word Line and Bit Line Select are turned on. The Storage Cell and its Bit Line charge-share, creating a slight voltage differential between the two Bit Lines.
4. The Sense Amp is turned on, amplifying the voltage differential and refresing the Storage Cell.
5. Word Line, Bit Line Select, and the Sense Amp are turned off.

## 4Mx1 DRAM

This is a more realistic block diagram of a 4Mx1 DRAM. A DRAM is actually composed out of several independent blocks, each of which is divided into 4 quadrants.

The diagram shows 512 Storage Cells tied to each Sense Amp (256 above and 256 below). 512 Sense Amps and their Storage Cells (256 kbits total) are lumped together to form a quadrant. 4 quadrants form a block, and 4 blocks comprise the entire storage area of the DRAM.

In a read operation, 9 bits of the Row Address are fed simultaneously into all 4 Block Row Decoders, and 9 bits of the Column Address are fed simultaneously into all 8 Column Decoders. The 2 I/O Lines that emerge from the left and right sides of each of the 4 blocks (16 bits in all) are then fed into an I/O Selector. The remaining 2 bits of the Row Address (the Row Select) and the remaining 2 bits of the Column Address (the Column Select) determine which of the 16 bits is selected to be driven onto the output Q line.

In a write operation, the Row Select and the Column Select determine which of the 16 I/O Lines receives the data bit from the input D line; the selected block then writes the bit into the selected Storage Cell.

In the layout of a single quadrant, the Sense Amps and Storage Columns are typically distributed. In the above diagram, a single quadrant of a 4Mx1 DRAM is laid out in 4 groups. Each group contains 128 Sense Amps, and each Sense Amp has 512 Storange Cells (256 above and 256 below) connected to it. Storage Columns are typically interlaced to improve symmetry.

## 512kx8 DRAM

A 512kx8 DRAM can be derived from the same design as a 4Mx1 DRAM. Instead of the I/O Selector selecting 1 of the 16 I/O Lines, it selects 8 lines to output data to or receive data from the 8 D/Q lines.

## Fast Page Mode Timing Diagram

Because DRAMs separately buffer the Row and Column Addresses and internally read whole rows at a time, they support a mode called Fast Page Mode. In this mode the Row Address is loaded into the DRAM only once for reading and writing several bits in the same row. The above diagram shows 4 bits being read and 1 bit being written (all in the same row) using Fast Page Mode.

• The Row Address is read from the Address Lines into the upper half of the Address Buffer on the falling edge of Row Address Select (RAS/). (Each of the bits in that row forward their data to their Sense Amps.)
• The Column Addresses are read from the Address Lines into the lower half of the Address Buffer on each falling edge of Column Address Select (CAS/). For each address the I/O Selector selects a different bit, which is driven out onto the Q line (bits D0, D1, D2, and D3).
• Bit D4 is written into the same row at column address Col4.
• The Bit Lines must be precharged every time a new row is accessed. Precharging occurs when RAS/ goes high.
• Also note the Access Times illustrated in the diagram:
• Row Access Time: Minimum time from row address to data.
• Column Access Time: Minimum time from column address to data.
• Column Cycle Time: Minimum time from one data to the next.
• Precharge Time: Minimum time from end of one row access to the start of another.
• The Sense Amps act as a Row Cache:
• A small, 1 large block, direct-mapped cache.
• Data is available while a row is "open".
• Data vanishes when the DRAM is precharged.

• ## Storage Cell Layout

There are 3 commonly used layout designs for DRAM Storage Cells: planar, trench, and stacked.

### Planar DRAM Storage Cell

The Planar Storage Cell is built up from the substrate. The cell's capacitor is formed by a dielectric silicon dioxide layer that is laid down between the polysilicon cell plate and the substrate.

### Trench DRAM Storage Cell

In the Trench Storage Cell is built down into the substrate. A narrow trench (typ. < 1 micron wide) is dug several microns into the substrate and filled with polysilicon to form the cell plate. This increases the surface area of the silicon dioxide layer, increasing the cell's capacitance.

### Stacked DRAM Storage Cell

The Stacked Storage Cell is built up from the substrate as is the Planar Cell. The dielectric layer is partially sandwiched between two layers of polysilicon, yielding a large capacitive surface.

Most DRAMs manufactured today use Trench or Stacked Storage Cells.