Course Information
CS 294-4 - Intelligent RAM (IRAM)

Lectures: Mon 2:45-4:00; Wed,Fri 2:10-3:30, Room 505 Soda
Instructor: Dave Patterson, Professor
office: 635 Soda, e-mail:
phone: 510-642-6587
office hours: Wednesday 4-5
Admin. Asst: Patricia Bodin, 634 Soda, 643-7066,

IRAM Background

Microprocessors and memories are made on distinct manufacturing lines, yielding 10M transistor microprocessors and 256M transistor DRAMs. One of the biggest performance challenge today is the speed mismatch between the microprocessors and memory. To address this challenge, I predict that over the next decade processors and memory will be merged onto a single chip. Not only will this narrow or altogether remove the processor-memory performance gap, it will have the following additional benefits: provide an ideal building-block for parallel processing, amortize the costs of fabrication lines, and better utilize the phenomenal number of transistors that can be placed on a single chip. Let's dub it an "IRAM", standing for Intelligent RAM, since most of transistors on this merged chip will be devoted to memory.

Whereas current microprocessors rely on hundreds of wires to connect to external memory chips, IRAMs will need no more than computer network connections and a power plug. All input/output devices will be linked to them via networks, as will be other IRAMs. If they need more memory, they get more processing power as well, and vice versa--an arrangement that will keep the memory capacity and processor speed in balance.

A single gigabit IRAM should have an internal memory bandwidth of nearly 1000 gigabits per second (32K bits in 50 ns), a hundredfold increase over the fastest computers today. Off-chip accesses will go over 1 gigabit per second serial links. Hence the fastest programs will keep most memory accesses within a single IRAM, rewarding compact representations of code and data.

Course Content

This advanced graduate course re-examines the design of hardware and software that is based on the traditional separation of the memory and the processor. Without prior constraints of legacy architecture or legacy software, the goal of the course is to lay the foundation for IRAM; it could play the role that prior Berkeley courses did for RISC and RAID. As in the past, this is a true EECS course which needs a mixture of students with different backgrounds: IC design, computer architecture, compilers, and operating systems. The ideal student will have taken one of the prerequisites, enjoys learning from students in other disciplines, shows initiative to help identify important questions and sources of answers, and is excited by the opportunity to shape the directions of a new technology where many issues are cross-disciplinary and unresolved.

The first part of the course will consist of weekly readings with round table discussions followed by a short lecture to bring people of all backgrounds up to speed for the next topic. There will also be several guest lectures followed by extensive questions and answers. Students will take turns putting up the summary of the paper and conclusions from the discussions and lectures on the course home page. In the last part of the course we will break up into teams to work on related term projects, ideally with an interim milestone to make sure that the project makes sense and to make midcourse corrections in the projects. The end of the course will be a series of presentations of the results and then a final lecture where we determine our progress on IRAMs and what are the remaining steps and most promising directions. The home page at the end of the course should document our contributions to IRAM. There are no exams: grades are based on class participation and on the term projects.

I expect the course and projects will answer questions such as: