CS 294-4 - Intelligent RAM (IRAM)

Burger, Doug; Kagi, Alian; Goodman, James R. "Memory Bandwidth Limitations of Future Microprocessors," to appear in the International Symposium on Computer Architecture , Philadelphia, PA USA, May 1996.
Deering, M.F.; Schlapp, S.A.; Lavelle, M.G. FBRAM: a new form of memory optimized for 3D graphics. SIGGRAPH 94 Conference Proceedings, Orlando, FL, USA, 24-29 July 1994. p. 167-74.
Elton, B.H.; Miura, K. A vector-parallel implementation and statistical analysis of the bucket sort on a vector-parallel distributed memory system: lessons learned in the integer sort NAS Parallel Benchmark. IN: Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing . San Francisco, CA, USA, 15-17 Feb. 1995. p. 782-3.
Hennessy, J.L.; Patterson, D.A. Computer architecture : a quantitative approach 2nd ed. San Francisco : Morgan Kaufmann Publishers, 1996.
Johnson, P.M. An introduction to vector processing. Computer Design , Feb. 1978, vol.17, (no.2):89-97.
Miura, K.; Takamura, M.; Sakamoto, Y.; Okada, S. Overview of the Fujitsu VPP500 supercomputer. IN: Digest of Papers. COMPCON Spring '93 , San Francisco, CA, USA, 22-26 Feb. 1993 p. 128-30.
Nakanishi, M.; Ina, H.; Miura, K. A high performance linear equation solver on the VPP500 parallel supercomputer. IN: Proceedings Supercomputing '94 Washington, DC, USA, 14-18 Nov. 1994. p. 803-10.
Ohshima, S.; Furuyama, T. High speed DRAMs with innovative architectures. IEICE Transactions on Electronics , Aug. 1994, vol.E77-C, (no.8):1303-15.
Patterson, David A. "Microprocessors in 2020," Scientific American, 150th Anniversary Edition, vol. 273, (no. 3):62-67.
Przybylski, Steven A. New DRAM Technologies: A Comprehensive Analysis of the New Architctures, MicroDesign Resources, Sebastopol, California, 1994: 26-39.
Sites, Richard L.; Perl, Sharon A. "PatchWrx--A Dynamic Execution Tracing Tool," submitted for publication to SIGMETRICS , 1996.
Tarui, Y.; Tarui, T. New DRAM pricing trends: the bi rule. IEEE Circuits and Devices Magazine , March 1991, vol.7, (no.2):44-5.
Utsumi, T.; Ikeda, M.; Takamura, M. Architecture of the VPP500 parallel supercomputer. IN: Proceedings Supercomputing '94 ,Washington, DC, USA, 14-18 Nov. 1994 p. 478-87.
Wulf, W.A.; McKee, S.A. Hitting the memory wall: implications of the obvious. Computer Architecture News , March 1995, vol.23, (no.1):20-4.
Yang, Ken C-K.; Horowitz, Mark A.; "A 0.8 Ám 2.5 Gbps Oversampled Receiver for Serial Links," to appear in proceedings of ISSCC, San Francisco, CA USA, Feb. 1996.