On Friday November 21, 1997 about 30 CS152 students, TAs, and faculty took the bus to Intel. The group left at 9:15AM from Soda Hall. After a brief stop to buy batteries for someone's digital camera, we rolled happily down the highway.
Along the way, Tanya said she hadn't been on a field trip since grade school, and her parents wondered why they were paying all that tuition money for her to go on a field trip. (Or at least that's what this reporter recalls.)
We pulled into Intel's Main Headquarters at Santa Clara, about 10:30AM, where we had to sign in and have our bags searched. Unfortunately, they also confiscated our digital camera and even forbid photos in the library.
John Crawford, who we later saw was one of 18 Intel Fellows, gave us a short history of his 20 years at Intel. (That's 18 out of 63,000 Intel employees.) He started in software, having done an early Pascal compiler for the 8086, and then went on to lead microcode development and architectural specification of the 80386, Intel's 32-bit address architecture (IA-32). He is now heading the IA-64 effort, Intel's next generation.
He first showed us the Merced design team, the first chip to implement IA-64, which remarkably is located on the 6th and 4th floors of the Robert Noyce Building. We saw chip plots of the cache (7 million transistors!), the Merced floor plan, as well as lots of cubicles. It was tough to tell which doll was most popular: bunny-suited disco dancers or Dilbert.
At 11AM John Crawford talked about IA-64 and EPIC. In addition to the motivation for IA-64, we saw some of the early highlights of the architecture. They have been working on it for 5 years, with a major change of direction once HP joined the effort in 1993. Thus far we learned some about instruction encoding (3 instructions inside 128 bit instruction elements), that they will interlock and stall the pipeline on data hazards, and that they have 128 integer and 128 floating point registers. Crawford said that the instruction encoding was the second most controversial part of the architecture, and that although the researchers were against having interlocks, from an industrial perspective they absolutely had to have them. It also includes predicative execution to reduce the number of branches, an idea found on earlier processors (e.g., ARM and PA-RISC).
The one sentence summary of IA-64 is a new ISA in the VLIW-style with a more efficient encoding of instructions and the added restriction of binary compatibility so that programs can run correctly across different implementations of IA-64.
Marketing apparently believes VLIW has bad juju, as it was never mentioned on the slides. Hence Crawford and marketing invented the phrase Explicitly Parallel Instruction Computer (EPIC). Seems to this reporter that Very Long Instruction Word computers qualify as Explicitly Parallel Instruction Computers, and that 128-bit instructions are Very Long Instructions when compared to 32-bit instructions, but who am I to judge?
Since the first chip won't be out for 2 years, it appears that Intel marketing's plan is to reveal a little bit about IA-64 every few months. Not yet revealed are multimedia support, relative code size to IA-32, floating point formats, ... Stay tuned to learn what is the most controversial part of the IA-64!
It was great to hear the main talk of a conference that charged $1000 a person to attend just last month. Also, this certainly qualified as the 6th guest lecture for CS152.
Next up was Andy Rice (Cal '91), who talked about working for Intel. (Actually, first we ate a free box lunch.) He talked about Intel culture: everyone (include Andy Grove) uses cubicles, Constructive Confrontation (where the anyone can challenge anyone on ideas within a company), Intel's ability to turn on a dime as the market changes, and how exciting it is to be working on projects that are absolutely going to be a significant presence in the market. We also learned that the work week is basically 40 hours, and that you get started by them giving you important work to do.
Andy is also in charge of the Rotating Engineer program, where a small number of new college hires work at 3 places for 4 months before deciding on where they want to spend their Intel career. Send him email if you have a broad background and might be interested: andy_rice@ccm.intel.com.
Other highlights were that the core of Intel's business were the CS 150, 152, and EE 141, that he strongly recommended taking Technical Communication courses (E190), and that he encouraged students to get a broad background while an undergrad. Especially interesting was that he found that Berkeley EECS Bachelor's students were on par with Master's students from a certain nearby Junior University.
At 1 PM we saw the Intel museum, which has a great collection of historic hardware and software, as well as showing a giant microprocessor with caches execute instructions while giving personalities and voices to the different components of a MPU. I'll always recall that Indian accent when I see the instruction decoder. We also had another 6th floor tour where we talked to people in the cubicles.
At 2 PM Demitri Terzopolous talked about of recently developed multimedia applications. We saw the talk of the physics, and the idea that each animated object had its own intelligence to move in an animated space, but a dog ate his videotape so we couldn't see the demo. (Or at least that's what this reporter remembers in the darkened room after lunch.)
At 3 PM we departed Intel, and arrived at Soda Hall at 4:45, wiser for the experience.
