1 Evolution of Optical Lithography

There is presently little disagreement on whether optical lithography can carry the I. C. industry to the 150-130nm generation in feature size. However there are few predictions of straightforward evolution of optics to address the 100nm generation. In fact the options for reaching 100nm with optics are limited, and we believe the trends charted in Figure 1 will be followed. Fig. 1 is a revision of data presented in a 1991 SRC-sponsored white paper on the future of Lithography (the principle changes from the earlier data projections reflect the unexpected long-life of I-line optics, and the slow movement to deep ultraviolet (DUV). [1] The path to 130nm appears to be a combination of increase in numerical aperture, modest improvements in effective K1 values, and the development of 193nm sources, optics and resists. Sophisticated stage technology for rapid, accurate scanning of images is also necessary, in order to relax field size requirements and permit the needed growth in numerical aperture.

Several technical risks remain in the path projected in Fig 1, perhaps the chief of which relates to the life of optical elements under DUV radiation. The high intensities required in high-throughput scanning systems exacerbate the optical damage problem [2]. The development of CaF₂ optics for construction of elements experiencing high-intensity radiation would be a significant enabler for 193 scanning optics. This material could also be important in achieving the chromatic corrections needed for all-refractive optics, in the event the very stringent line narrowing and stability needed from the ArF laser for monochromatic operation cannot be obtained.

Can Optical Lithography Reach 100nm?

Given the amazing record of optical lithography in going beyond a number of previous "fundamental limits", one would be foolish indeed to predict the demise of optical lithography. In fact there are a number of ways known even now to get to 100nm, and possibly slightly beyond. For example:

1. A breakthrough in mostly reflective optical design together with the development of a robust F₂ laser (157nm) would enable evolution to 157nm, and bring the minimum feature size down to 100nm for a scanned system. Or
2. If a liquid immersion optic with NA in the range of 1.1 were designed and accepted, 100nm would be reachable at a wavelength of 193nm. (However the very high speed scanning required with small-field optics would appear to be incompatible with liquid between the optic and the wafer.)

On the basis of present progress in conventional DUV optics, it is reasonable to predict the availability of optics with specified resolution of 120nm by the year 2005. The develpment of very high NA two-dimensional scanning tools would further reduce minimum feature size, but such development is not a sure thing, thus predictions beyond this feature size and time frame are more difficult.

2 Technology Options Beyond the Conventional Optical Limit

There are a number of technologies at various stages of development aimed at potential replacement of optical lithography. In decreasing order of demonstrated technological capability they are

1. E-beam lithography
2. X-ray lithography
3. EUV lithography
4. Ion-beam lithography
5. Various approaches to maskless lithography

The order of this list, certainly somewhat subject to debate, would change if productivity factors such as cost of ownership, mask availability, throughput, and so forth were included. For example conventional e-beam lithography, a tried and true technology capable of writing very small features, has a fundamental problem in achieving high throughput. There are today few advocates for e-beam as a general purpose patterning technology. Even the developers of cell and character projection systems see severe throughput difficulties in the 100nm feature size regime. (Newer forms of e-beam lithography such as SCALPLE can potentially address the throughput issue, but introduce significant additional technical risk, at least comparable to other candidate technologies.)

If we use the level of industrial support as a measure, two technologies are clearly favored at this time, namely X-ray lithography and EUV lithography. Both are under intensive development, especially in the United States. Smaller, but significant, efforts are underway in Japan and Europe. The SCALPEL project at Bell Laboratories, and the cell projection program at Hitachi are the major development efforts in e-beam lithography for manufacturing. The ion-lithography effort led by the group in Vienna has been slowed by a decrease in funding, although a new European-based funding source appears on the horizon. There are a number of other approaches to general-purpose lithography which are only in the research stage. In particular there are several approaches to maskless lithography, depending to various degrees on parallel arrays of writing instruments. The most modest approach, arrays of up to about one hundred mini electron columns, has moved from IBM Research to ETEC. Research at Cornell and Stanford is aimed at exploring much larger arrays, involving possibly thousands of parallel beamlets. The rapidly developing MEMs technology, using both single crystal Si and polycrystalline films to construct arrays of microstructures makes possible a wide variety of writing approaches. One example is the Stanford work on lithography with arrays of AFM/STM tips. Another is the MIT proposal to make arrays of shutters for soft X-rays, and focus the beams with zone plates. Yet others would use arrays of moveable micromirrors to modulate optical beams at suitable wavelengths (such as in the EUV region). Clearly the various technologies are at quite different stages of development, something to keep in mind in the brief discussion which follows.

3 X-Ray Technology

X-ray lithography has demonstrated compatibility with high volume manufacturing facilities, an ability to yield modern high-density circuits, and resolution of 100nm and below in useful devices and circuits. The infrastructure necessary for widespread industrial use is beginning to form, but is not yet in place. The most significant programs are in Japan. In this country, Motorola and IBM are the only SIA members with active x-ray programs. XRL has matured to a stage where with further engineering, particularly on the mask, insertion in ULSI manufacturing can occur early in the next decade.

What has been done with x-ray lithography:

For several years XRL has been used to produce high performance devices and high density circuits, some at 100nm and below. Most of the sub-100nm work has been done in universities [3,4]. Researchers at NTT in Japan have used XRL to fabricate complex chips, including fully functional LSI CMOS circuits at 200nm on SIMOX with 20nm (3s) CD control [5]. At the1996 IEDM NTT reported a 240nm-pitch 4-G DRAM array using XRL [6]. IBM has fabricated fully-functional 512K SRAMs with 6 million transistors, and 64Mbit DRAM chips with bit yields of better than 99.9%, establishing the suitability of XRL in a production worthy Si fabrication facility [7]. More recently, logic test chips with 80nm minimum features were fabricated. CMOS ring oscillators on SOI with 100nm gates were fabricated with XRL and had a room temperature delay per stage of 15psec at 1.5V.

Motorola processed several 1Mbit SRAM lots with 350nm ground rules, exposing up to three critical levels with XRL. Some of the lots had fully functioning SRAMs with yields comparable to I-line lithography, demonstrating that x-ray masks can be fabricated and used for complex circuits. Each x-ray exposure field contained four 1Mbit SRAM circuits with more than 5 million transistors per circuit. At the 1995 IEDM meeting, Mitsubishi reported on the fabrication of memory cell arrays for 1Gbit DRAMs at 140nm minimum feature size using XRL [8]. An exposure latitude of 22% and 3s CD control of 14nm were achieved. XRL has long been used in the fabrication of devices pushing the state of the art in feature size . [1] Figure 2 shows a recent example, the fabrication of coulomb blockade devices, with feature sizes well below 100nm.

One of the unique advantages of XRL is "absorption without spurious scattering". Since the index of refraction of all materials are very close to unity at x-ray wavelengths, there are essentially no reflections at interfaces, and hence no standing waves, no notching, and no need for antireflection coatings, tight control of resist thickness, or surface-imaging resist. The well-known wide-process-latitude of XRL is in large measure a consequence of absorption without spurious scattering

The work to date demonstrates some of the important advantages of XRL, including its fundamental simplicity. The remaining engineering problems in bringing about 100nm XRL in manufacturing are all relatively well understood. The major uncertainties are related to the mask, its freedom from distortion, its patterning, and the creation of an infrastructure that can supply masks to the semiconductor industry at the right price and the right turn-around time.

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The x-ray source and beam line - The optimal source for manufacturing with x-rays is a synchrotron. Synchrotrons designed for XRL are available from two commercial suppliers: Oxford Instruments and Sumitomo Heavy Industries. Both recently unveiled second-generation machines. The commercial synchrotrons are highly reliable, operating with better than 95% uptime, with no major problems or extended downtimes. A single synchrotron can accommodate 10 to 20 mask aligners, connected to the synchrotron via "beam lines". New beam-line designs can deliver 50-70 mW/cm² over an area 50 x 50 mm, corresponding to an exposure time of about 1 sec for field sizes exceeding 10cm².

The aligner and the overlay budget- Aligners for x-ray lithography are available commercially from SVGL, Suss Advanced Lithography (SAL), and Canon. The requirements on aligner stage performance are substantially the same for XRL as for example, for alignment of the aerial image to the wafer in optical lithography. The mask and substrate are immersed in a helium atmosphere which enables efficient temperature control. Table 1 illustrates the tolerances that must be achieved by the various components of an XRL system and process. An approach for magnification correction is presently under investigation at IBM.

The mask - The mask is the cornerstone and the most daunting challenge of x-ray lithography. Recently, a consensus has emerged in the USA with regard to masks for Si ULSI manufacturing. Discussions among Japanese and US developers may result in an agreement on an international x-ray-mask standard.

The absorber pattern geometry is defined by electron-beam lithography. As with all types of masks, the e-beam writing time becomes very long, and data handling more complex, as we approach the 1-Gbit generation and beyond. The importance of reducing the e-beam contribution to linewidth and overlay error is evident from Table 1. The Leica EBPG has demonstrated 25 nm 3-s placement accuracy over a 2.5x2.5 cm field, making it the only commercial tool compatible with 150nm features. The tool's major limitation at this point is throughput. The work on spatial-phase-locked e-beam lithography offers the potential for significant improvements in e-beam placement accuracy, down to the nanometer level [9].

Equipment to effectively address the persistent problem of defects in XRL masks is available. Inspection of x-ray masks is done with the electron-beam SEMSPEC, manufactured by KLA. This tool is adequate down to 100nm features. Repair of x-ray masks is done with focused-ion-beam tools, of which there are three manufacturers: Micrion, FEI, and Seiko. X-ray masks can be purchased in research quantities from IBM Burlington and NATC (a commercial spin-off from NTT). Clearly, these vendors and perhaps others will have to scale up for volume production before manufacturing would be feasible.

Bits/ DRAM	1-Gb		4-Gb
Generation	1st	Shrink	1st	Shrink
CD(nm)	180	150	125	100
OVERLAY CONTRIBUTIONS (LEVEL-TO- LEVEL)
Illumination	6	5	4	4
Aligner	40	33	27	22
E-beam writing	32	25	22	17
Mask residual	12	10	8	8
Wafer/resist	12	12	10	10
OVERLAY TOTAL (nm)	54	45	38	30
LINEWIDTH CONTRIBUTIONS
Illumination	4	4	4	3
Aligner	3	3	3	4
e-beam writing	14	12	10	8
Mask residual	5	4	3	3
CD TOTAL (nm)	18	15	13	10

Extendibility - XRL can support several generations of linewidth, with modest evolution. Extendibility below 100nm requires that the mask-sample gap can be reduced below 15mm. This is illustrated in Fig. 3 which tracks the gap needed as linewidth is shrunk. The same synchrotron, beamline, stepper, mask structure (and possibly even resist) can be used at 100nm, 70nm and somewhat beyond. Each generation will most likely see the introduction of steppers and masks that provide better overlay, but all generations can be based on the same basic approach and techniques. As with any technology reduction of feature size will require advances in e-beam mask writers; mask inspection and repair tools; precision stages and aligners; mask materials, resists and metrology.

3 EUV Technology

EUV lithography can be viewed as an extension of optical projection as illustrated in Fig 4 where it is compared to DUV projection lithography. Specific wavelength choices in optical lithography have always been driven by fortuitous technological options afforded by nature (such as the spectral lines of mercury or the excimer laser lines). EUV lithography is no exception. In this case, the high normal incidence reflectivity of Mo/Si multilayer reflection coatings at 13 nm is the key driver for the choice of the EUV wavelength. This particular combination offers the highest normal incidence reflectivity (>65%) at any wavelength below 120 nm (although very recent work suggests that Mo/Be coatings could provide even higher reflectivity at 11 nm). By making such a large jump in wavelength from the UV region, it becomes possible to dramatically relax the NA needed to reach the 100 nm feature size. While 193 nm lithography lenses will likely evolve to NA exceeding 0.7, EUV optics require NA of only about 0.1 to reach 100 nm resolution. This makes it possible to design relatively simple all-reflective optical systems with only a few (~4) elements. An additional benefit of the short wavelength (and consequent low NA) of EUV systems is that the depth of focus is large, in excess of one micron.

In this country, development of EUV technology is currently supported primarily by an industrial consortium led by Intel, known as the EUV LLC, with work being performed by a unique collaboration among lithography equipment suppliers, semiconductor companies, universities, and government laboratories. Small but significant efforts are also underway in Japan and Europe.

EUV lithography involves several major technical challenges. Recently however, dramatic progress has been achieved in all of the major issues, suggesting a clear engineering path for development. The major issues which have been addressed include the source, the mask, the optics, and the resist.

Source- Based on the best current understanding of achievable mirror reflectivity, condenser/projection optics design, and resist sensitivity, a requirement for source power can be established given a particular throughput requirement. The exact value depends on the details of the design, but for a throughput of 30 (200 mm diameter) wafers/hour, it is somewhere in the range of 10 W into a bandwidth of about 2.5 Å. The leading candidate source technology is a laser driven plasma source. Work at Sandia National Laboratory [10] has shown that conversion efficiency from a suitable pulsed laser, (such as Nd:YAG) to in-band EUV radiation is ~1%. This leads to a requirement on the driver laser power in the range of ~1 kW. Such a laser is not currently available commercially, but the technology involved is well understood and its development should be straightforward. The other issue with a laser plasma source is debris from the plasma, which can deposit on the condenser optics, and degrade their reflectivity. Sandia has developed a gas jet target [10] which virtually eliminates this problem.

The mask - As shown in Fig. 4, the mask for EUV lithography is a reflection mask with 4X reduction. The use of a reflection mask on a robust, thermally and mechanically stable substrate is a significant advantage of EUV technology over alternative technologies which require membrane masks. Reduction, of course, is an additional advantage relative to 1X masks, as it relaxes requirements on mask CD control and image placement accuracy. The mask blank is a flat, with a multilayer reflection coating. A thin absorber layer is deposited on top of this blank and patterned in order to produce the finished mask. Given a perfect mask blank, conventional mask inspection and repair strategies can be used for the patterned absorber layer. However, there is a technical challenge in producing and inspecting a defect-free blank, in part with respect to defects within the multilayer reflection coating itself. This coating consists of circa 80 deposited layers which must be very nearly defect-free. (Absolute perfection is probably not required since a few small defects can be arranged to be covered by the absorber pattern.) This would appear to be a highly daunting task, but recently, using a special ion-beam sputter deposition system specifically designed for this purpose, researchers at Lawrence Livermore National Laboratory have demonstrated [11] the capability of high yield fabrication of 6" reflection mask blanks with <0.03 particle defects/cm², where defects larger than 130nm were counted. In this work, particle defects were detected using standard wafer particle scanning equipment, which may not fully reflect defects which print at 13 nm. At-wavelength testing of these blanks is expected to be performed within the coming year.

Optics - Achieving diffraction limited imaging performance is the major challenge in EUV lithography optics due to the scaling of wavefront aberration tolerance with wavelength. This challenge is compounded by the necessity of use of aspheric surfaces in EUV projection optics, in order to achieve the needed field size and distortion specifications, using only a small number of mirrors. Total wavefront error and surface figure error specifications are in the 0.1 - 0.5 nm range. These very small error tolerances represent a challenge not only for optical fabrication, but also for wavefront and surface figure metrology. Yet, here again, recent progress has been dramatic, and engineering solutions are now at hand. A set of aspheric mirrors produced by Tinsley Labs for a prototype EUV camera at Sandia National Laboratory 12] achieved surface figure error very close to the required accuracy (<0.6 nm rms).

On the metrology front, progress has been dramatic as well. Phase-measuring diffraction interferometry has been successfully applied in both the visible [13] and EUV wavelength ranges [14], reaching accuracy levels in wavefront metrology of 0.5 nm or better. "At-wavelength" interferometry has been found to be essential as lithographic optics have scaled to shorter wavelengths, and this would appear to be a particularly difficult challenge at EUV wavelengths, due to the lack of a laser source. However, using an undulator source at the Advanced Light Source synchrotron facility at Lawrence Berkeley National Laboratory, a suitable interferometer has been successfully built and operated. An example result is shown in Fig. 5.

Photoresist - At EUV wavelengths, absorption in organic materials is very high, similar to that at 193 nm. Thus, surface imaging techniques are the leading candidates for EUV lithography. These techniques are now being heavily developed for 193 nm lithography, and EUV will directly benefit from that effort. Promising results at EUV wavelengths using a silylation process have been reported by Sandia National Laboratory [15].

Extendibility - EUV lithography offers the potential to continue the extension of optical projection lithography for many generations beyond 100 nm, probably down to the ultimate physical limits of CMOS technology. Figure 6 shows how the NA and depth-of-focus evolve for EUV lithography all the way down to 25 nm feature size, for two candidate EUV wavelengths. This figure was calculated assuming a K₁ factor of 0.6, and a K₂ factor of 1.0. These factors are indeed quite conservative considering the time frame being discussed here. It is quite likely that resolution enhancement techniques will be highly developed by the time that EUV lithography comes into usage, and K₁ factors below 0.5 will be possible. A demonstration of the use of attenuating phase-shift masks has already been reported in EUV lithography [16].

Process Integration - As a demonstration of integration of all of the necessary elements of an EUV lithography system, and to enable further exploration of the application of EUV lithography, a "micro-stepper" system has been constructed at Sandia. This system incorporates a wafer stage alignment system, enabling level to level overlay, and hence device fabrication. Successful fabrication of NMOS transistors with gate length down to 100 nm has been demonstrated [17].

4 E-beam Technology

The history of electron beam tool development provides some insights into the future. For instance, despite many years of intense development, single beam gaussian and shaped beam tools have not made significant progress toward becoming robust manufacturing systems; if anything, these tools have not kept up with the pace of optical tool development, and are less competitive today than they were a decade ago. The problem is a result of the fact that, in manufacturing, the effective number of pixels (which would have to be processed by gaussian beam tools) has been increasing exponentially at rate doubling every 3 years. A similar statistic applies to the number of individual shapes which would need to be drawn by shaped-beam tools. Despite major electron beam technology improvements such as thermal field emission cathodes and chemically amplified resists, conventional electron beam technology has not kept pace. Thus, a reasonable conclusion is that further evolutionary advances of these tools (better sources, faster deflection, cell projection) will not provide a manufacturing solution. Revolutionary technology developments are required. One such approach is the SCALPEL program at Bell Laboratories [18]. In SCALPEL electrons pass through a membrane (4X) mask and those not scattered by the patterned scatterer layer are imaged on the wafer. Mask heating is fundamentally minimized by using the mask in scatter rather than absorption mode, and large fields can be accommodated by synchronous scanning of mask and wafer. A proof of principle system has been constructed and showed excellent high-resolution imaging [18]. Further work towards construction of a prototype lithography tool is presently underway at Lucent.

Other approaches to revolutionary e-beam lithography use multiple beams to increase throughput. The multiple beam approaches can be subdivided into two categories - multi-source [19], where multiple beams are generated in a single optical column; and multi-column [20], where each beam has its own individual (micro)column. These approaches are illustrated schematically in Fig. 7.

Multiple beam electron beam technology --Unlike SCALPEL, the multiple beam technologies have the advantage of being maskless techniques - they transform computer data directly into printed images. The two generic approaches to multiple beam lithography illustrated in Fig. 7 trade off advantages and disadvantages. Both systems require a blanking signal for each beam. Having a separate optical column for each beam will almost certainly entail separate alignment, scanning, and focus electronics for each beam as well; the electronics and wiring issues for hundreds of such beams becomes an enormous practical issue. Calibration of every beam likewise will be a major obstacle, and overall system reliability will be challenging. If the electron sources and the optics are fabricated using MEMS technology, it might be possible to insure extraordinary uniformity, easing the alignment/setup problems. An example of such an array of tips and columns is shown in Fig. 8. This array, fabricated by Prof. Noel MacDonald's group at Cornell, has all the elements constructed from single crystal silicon and embedded insulators.

If instead of individual columns all the beams share the same set of optics, great simplification occurs. However, space charge problems of both stochastic beam blurring and pattern dependent beam position errors limit the total current to a few microamperes which results in throughput limitations and severe resist sensitivity requirements. Also, calibration of the focus, astigmatism, and position of individual beams is not possible, which may lead to resolution degradation at the field edges due to lens aberrations, as well as uncorrectable errors in individual beam positions due to source manufacturing limitations.

Looking at the positive issues for each, the multi-column approach allows individual calibration of each beam for potentially higher accuracy and there are no space charge limits to the number of beams or total current, and no beam-to-beam uniformity issues due to lens aberrations. For the multi-source approach, the control electronics is much simpler; beam position stability between calibrations will be better (since all beams share the same optics, and the beams are much closer in space), calibration is much simpler, and reliability should be much less of an issue since the beams share a common cathode and electronics.

Beam voltage tradeoffs - Because the multi-column architecture is fundamentally a low voltage approach, while SCALPEL and the multi-source architecture are more likely to be used in a high voltage system, it is important to understand the issues related to beam voltage. Low voltage (<3KV) has the distinct advantage of avoiding the proximity effect by reducing the scattering length of the electrons to less than the minimum feature size. This implies that the active resist thickness also must be less than the minimum feature size, and that the aspect ratio in resist be less than 1. In practice, 100 nm groundrules will probably allow a maximum imaging layer thickness of 50 nm. Transferring the pattern into the substrate thus becomes problematic. Although a number of bi- and trilevel resist systems have been developed, none has entered into manufacturing. Top surface imaging resists have been developed for optical lithography, but rarely used. For low voltage electron beam lithography, a conductive discharge layer will be required. Pinhole defects in the thin resist imaging represent a largely unknown risk. Clearly more research is required.

High voltage (> 20 KV) has the advantage that the electrons experience less forward scatter in the resist, leading to straighter sidewalls in thicker resist. This bulk exposure allows fabrication processes similar to conventional optical processing, where a relatively thick single layer resist is used directly as a mask for etching the underlying layers. The maximum aspect ratio that can be fabricated for deep sub-micron features has been shown to be related to the accelerating voltage. However, high voltage exposure will require proximity effect correction. X-ray mask work at IBM has demonstrated that dose correction is a tractable problem even for large chip sizes [21]. Unfortunately, SCALPEL will require correction either by feature size adjustment or by GHOST [22] which result in poorer linewidth control relative to the dose correction method. Because resist sensitivity decreases with increasing beam voltage, the energy deposited in the substrate increases roughly as the square of the accelerating voltage. The energy deposited in a silicon wafer due to electron beam exposure at 100 KV is enough to raise its temperature 2-4 degrees if there is no loss due to radiation or conduction. Such a temperature change would lead to unacceptable placement errors if correction schemes were not implemented.

Space charge effects -- Electrons mutually repel each other, and in high current systems this can seriously degrade the resolution of the system. The system architecture has a major influence on the extent of the interaction. As the spacing between electrons increases, the maximum beam current for a given resolution increases. We can look at a progression of system architectures in terms of the severity of space charge effects, starting with single round beam systems (the worst), shaped beam, cell projection, multi-source, SCALPEL, and final multi-column, where interaction between electrons in neighboring columns is essentially non-existent. Experimental results have shown that space charge effects limit shaped beam and cell projection techniques to about 1 µA of maximum total current at 50 KV. Initial simulation work shown in Fig. 9 indicates that multi-source approaches can reach 5-10 µA of total current at 50 KV. Simulations indicate that SCALPEL is limited to 20-40 µA total current (equivalent to 10-20 µA at 50 KV). Multi-column designs are limited only by the number of columns that can be integrated into a tool. Since 10 µA at 50 KV is the current needed to achieve a throughput of about thirty 8î wafers/hour, it is crucial that the simulation work explore all possible parameter variations in order to optimize the maximum current. It is also crucial that the simulations be confirmed with experimental data.

Cross-cutting technological issues-All the approaches to e-beam lithography would benefit from further research in sources, beam interactions and resist materials. Stable, uniform, high brightness cathodes are a common need for all technologies. Photocathodes have proven their performance in night vision devices for military applications and initial research has shown that these cathodes have characteristics (high brightness, low energy spread, low noise) that make them ideal candidates for lithography and metrology. In addition, the large, uniform emission area make them an enabling technology for many multi-source applications. They may also play a role in SCALPEL and multi-column approaches.

Space charge effects will play a role in any high-throughput electron beam technology. Current analytic models are inadequate to describe the various proposed multi-beam configurations. Simulations are time consuming and lack experimental verification. Experimental verification is required to confirm the predictions of both the analytic models and the simulations. Understanding the tradeoffs related to beam voltage, multi-beam spacing, and system architecture are crucial in order to achieve the optimum system configuration.

High resolution, high sensitivity resists represent another opportunity that requires further research before the limits are understood. Assuming reasonable quantum efficiency, the best current resists are at least an order of magnitude away from shot noise limits to sensitivity. Development of faster resists would ease the limits on throughput imposed by space charge effects and could allow the use of simpler system architectures that would otherwise be prohibited due to space charge limits on total beam current.

5 Other Maskless Lithography Technologies

There are several attractive features unique to maskless lithography. The cost of fabricating, inspecting, maintaining, and cataloging masks, and the potential for yield loss associated with any errors in the mask management process are significant driving forces toward elimination of the mask. Comparing conventional pelliclized optical lithography with X-ray and EUV technology suggests higher defect control discipline would be required for the latter, aggravating an already difficult problem in the deep submicron regime. On the other hand, defects must still be controlled in maskless lithography. The absence of a mask eliminates only the "repeating killer" defect, not all defects. A second feature of maskless lithography is the potential availability of a continuum of layout variations. This could be exploited in process development, device and circuit development, yield studies, customization of "low runner" designs, and in general in any development situation where exploration of a continuum of process parameters could be useful. Any maskless technology is also a candidate for a higher performance pattern generation technology for fabrication of masks or reticles for technologies requiring them.

MEMS technology makes possible a number of maskless approaches to lithography beyond simple arrays of e-beam columns. The demonstration of lithography using parallel arrays of proximal probes by Prof. Cal Quate's group at Stanford is an impressive example. In this case probes operated in a combined AFM/STM mode are rapidly scanned over the surface to be patterned. Figure 10 illustrates the throughput which can be achieved with highly parallel arrays, and Figure 11 shows devices constructed with arrays of 4 tips, moving at speeds up to 3mm/sec. Interestingly, the writing speed to date is not limited by energy transfer, but simply by mechanical control and stability, leaving room for significant speedup. Problems under investigation include tip wear, automatic control of tip altitude, and sensitive resists for high-resolution patterning.

Prof. Hank Smith's group has proposed an array of shuttered zone plates, shown in Figure 12, which focus and modulate X-ray beams, with wavelength chosen for optimization of resolution and resist compatibility. Research is only beginning on this novel scheme, and will investigate both the MEMs aspects and the "optical" issues such as illumination.

Discussion

Present industrial strategy appears to favor the early choice of the most promising choice for 100nm technology, with concentration of the majority of development money on this technology. Given the assumption that 100nm technology is needed for development early in the next decade and for prototype manufacturing around 2005 , tool development must begin rather soon. Forcing the technology decisions onto such a schedule does not permit a normal research phase with orderly progress in risk reduction. Technologies with relatively uncertain risk, despite highly attractive features and potential low cost cannot be considered. Thus the tool development scenario most likely to take place is the full-scale development of either an X-ray, EUV, or e-beam (SCALPEL) tool, with a relatively low-level research effort in parallel to explore future alternatives. We believe that the cost, simplicity, extendibility, and flexibility advantages of the future maskless alternatives are compelling. Certainly their introduction into manufacturing will be delayed by the enormous focus of effort required to make one of the mask technologies work. But the inherent advantages of maskless lithography, combined with the rapid progress taking place in MEMS fabrication technology, will make the eventual introduction of a highly parallel, maskless lithography inevitable.