1	The MARCO/DARPA Gigascale Silicon Research Center Overview and Progress Report DARPA Kickoff Workshop Washington, DC December 6^th, 2001
2	The Productivity Gap
3	Implications of Not Doing the Research If we do not solve these long-lead-time problems: Accelerated slowdown in design productivity Increasing unpredictability in design cycle Inability to verify/correct complex designs Major NRE cost increase for complex designs (likely anyway!) Which leads to: Expensive chips—large markets economically inaccessible Inability to guarantee hitting market window Quality issues in the field Overall industry slowdown
4	“It’s a Moonshot, Not Rocket Science”
5
6
7
8	What Would “Success” Look Like? Design implementation with predictable, microprocessor-quality components on an ASIC schedule Emphasis on efficient, predictable, cost-effective component implementation strategies Role of reuse and communication-based assembly and verification approaches Emphasize energy and power management Building highly-reliable systems from unreliable/unpredictable components and technologies Accurate statistical characterization of process and its circuit-level implications New circuit design styles to accommodate the above Integration with test, diagnosis and self-repair, including analog
9	What Would “Success” Look Like? Enable programmable solutions through programming support for complex, programmable IC’s A natural programmer’s model that allows for efficient utilization of the platform for a variety of applications Emphasis on exploiting and managing concurrency in the application and its implementation Develop a solution (methodology and technologies) for the effective and reliable exploitation of concurrency in the design and correct implementation of hardware and software-based single-chip systems and their interfaces
10	www.gigascale.org : A Critical and Effective Resource Example: August 2001 56,541 accesses 400,841 hits Average visit 3 pages Served 755 Mbytes Broad range of users: 29% from com 9.2% from edu 1% from mil, gov 21% overseas: 63 countries France, Canada, Finland, Netherlands, Germany, Hong Kong, Japan heaviest visitors
11	GSRC Website Statistics: July 1999 – August 2001
12	The Gigascale Silicon Research Center http://www.gigascale.org
13	Overarching GSRC Research Emphasis for 2001—…? : “From Ad-Hoc System-on-a-Chip Design to Disciplined, Platform-Based Design”
14	The Gigascale Silicon Research Center http://www.gigascale.org
15	What is a Platform? Broadly stated, a Platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer A Platform is a coordinated family of hardware-software architectures, that satisfy a set of architectural constraints, imposed to allow the re-use of well-characterized hardware and software components and technologies. New platforms will be defined at the architecture-microarchitecture boundary They will be heterogeneous and component-based, and will provide a range of choices from structured-custom to fully programmable implementations
16	The Chip-Level Implementation Gap
17	The Chip-Level Implementation Gap
18	Tradeoffs and Reuse Model
19	Disciplined, Platform-Based Approach
20	Current Scenario–ASIPS on the Rise in Networking
21
22	The Keys to A Productive Future: “The Three R’s”
23	Regularity & Physical Design New design regularity has been the enabler for every quantum step in design automation and design productivity But DSM physical synthesis can not take us all the way to affordable gigascale w/o additional forms of regularity! Beyond MOSFETs, FINFETs, ..., we expect that logic patterns and implementation platforms will become more even regular—via self-assembly
24	DSM ASIC Implementation and Manufacturing Part of our research has been to understand, model and create forms of regularity to overcome DSM problems that include: Printing and manufacturing high yield silicon with nanometer feature sizes Creating reliable designs with component parameters that vary substantially Distributing power reliably and guaranteeing signal integrity Structured communication channels and/or clocking methodologies Providing accurate prediction capabilities for system-level exploration from the Architectural Platform level Facilitating reliable design signoff for guaranteed first-pass success
25	SIP Design System
26	Platform Design Methodologies: Platform Stacks
27	A Discipline of Platform-Based Design
28	From Methodology to Silicon
29	GSRC Themes for 2001
30	Verification: Self-Checking Microprocessor Add checking and recovery logic to microprocessor Makes sure each instruction gets correct operands and results Simple hardware can operate at full processor speed Don’t need result of one instruction before starting another Correct results when needed Can be slow
31	Benefits of Self-Checking Validation By verifying the checking/correction logic, we can guarantee correct behavior by overall system Much smaller task than verifying entire system Embedded Software Is a critical part of the overall validation problem and will play an increasingly important role in our research. We will most likely tackle it in the context of a family of platforms. Reliability Reduced sensitivity to transient effects such as radiation events
32	New Test Paradigm: Embedded SW-Based Self-Testing & Mixed-Signal BIST
33	Research Agenda–GSRC Test Theme Embedded Software-Based Self Testing Platforms and methods for systematic design of embedded software (SW) self-tester System-level DfT techniques to support SW-based self-test Embedded SW-based self-diagnosis Embedded SW-based defect characterization Analog/Mixed-Signal Self-Testing DSP-based self-testing of analog/mixed-signal components Self-testing of high-resolution (³16 bits) converters On-chip measurement for high-speed serial communication links
34	“Power and Energy in Design” – Vision (Joint with Interconnect FCRP)
35	Classification and Quantification of Power Management Techniques as a Function of Activity (Active + Standby)
36	“Living ITRS-2001” in GTX First time ever: consistency checks, unified assumptions for power, frequency, die size, density, performance Creates linkages between Design, Assembly/Packaging, Defect Reduction, Process Integration / Devices / Structures, Test, Overall Roadmap Technology Characteristics, … Models and studies are linked with ITRS-2001 distribution Improves flexibility, quality, transparency of roadmapping Allows semiconductor industry to better allocate R&D investment: “Who should solve a given red brick wall?” 2002 goal: Increase fraction of ITRS captured within GTX
37	“Living ITRS” Example Study: Maximum Chip Area Containing High-Performance Logic (PIDS Chapter), Subject to Power Limits (Assembly/Packaging Chapter)
38	A Discipline of Platform-Based Design
39	Relationship to Other FRCs and Future Plans
40	“It’s a Moonshot, Not Rocket Science”
41	“Not Just Research As Usual” The GSRC is a unique experiment in long-range, collaborative research, enabling broad collaboration across many areas of EDA and Design In the 1960-1980’s DARPA played a key role in creating and maintaining a collaborative community in design and architecture Xerox PARC & the Alto, Berkeley Unix, RISC, RAID, Integrated EDA Systems… GSRC is about rebuilding and maintaining such a community of researchers in many fields related to design productivity By leveraging modern, distributed collaborative infrastructure By enabling and supporting a series of research themes By developing and maintaining a well-defined, but broad goal—the Moon Shot—that serves to integrate all participants